The 68HC05 central processor unit (CPU) consists of an accumulator (A), an index register (X), a stack pointer (SP), a program counter (PC), and a condition code register (CCR).
Data can be read from memory into the accumulator and the index register. Likewise, data can be written into memory from the accumulator and the index register. The accumulator, however, is the only register upon which arithmetic and combinatorial logic operations can be performed. Only the index register can provide user-generated effective addresses for operands read into or written from the accumulator. Both the accumulator and the index register support bit-wise shift and rotate operations.
Most accumulator, index register, and memory operations affect status flags in the condition code register. The carry bit is set when an arithmetic carry or borrow has taken place. Shift and rotate operations also move bits through the carry bit. The zero flag is set when all bits of an operand or result are zero. Likewise, the negative flag is set when the MSB of an operand or result is one. The I bit masks interrupts and is set during interrupt processing. Software can also set and clear the I bit. To facilitate BCD arithmetic, the half carry flag is set when a carry from bit three to bit four of an operand occurs as the result of an ADC or ADD instruction.