| Addressing Mode | Supported in HC05's | Supported in HC08's | Description | Example |
| Inherent (INH) | Yes | Yes | Single byte(1) instruction whose operand is inherent in the instruction and not explicitly stated. | CLRA, INCX, RTS |
| 8-bit Immediate (IMM) | Yes | Yes | Operand is the single-byte data following the opcode. This data is a value rather than a reference to a value (address where a value is stored). | STA #$80 |
| 8-bit Direct (DIR) | Yes | Yes | Operand is the single-byte address following the opcode. This address in page 0 memory ($00-$FF) is the storage location of the data operated on. (2) | CMP $50 |
| 16-bit Extended (EXT) | Yes | Yes | Operand is the two-byte address following the opcode. All legal addresses above $FF in the memory map can be accessed with this addressing mode. | STA $E000 |
| 8-bit Relative (REL) | Yes | Yes | Operand is the single-byte signed value following the opcode(3) . This addressing mode is used only for branch instructions with most of these being conditional upon the state of a condition code register flag. The operand can specify a branching range from -128 to 127 bytes away from the current program counter value. | BNE BRANCLOC
(BRANCHLOC WITHIN ALLOWABLE RANGE) |
| 16-bit Indexed, No Offset (IX) | Yes | Yes | Single byte instruction like inherent addressing but whose operation is more like the direct (for the HC05) or the extended (for the HC08) mode. Rather than the data's address following the opcode, the inherent operand is the 8-bit address in the X register for the HC05 or the 16-bit address in the H:X register for the HC08. | LDA , X |
| 16-bit Indexed, 8-bit Offset (IX1) | Yes | Yes | Same as indexed, no offset but with an 8-bit unsigned offset contained in the byte following the opcode. Referenced address is formed by adding the 8-bit offset to the content of X (for HC05) or H:X (for HC08). | LDA #OS8B, X |
| 16-bit Indexed, 16-bit Offset (IX2) | Yes | Yes | Same as indexed, 8-bit offset but with a 16-bit unsigned offset contained in the two bytes following the opcode. | STA #OS16B, X |
| 16-bit Indexed, No Offset with Post Increment (IX+) | No | Yes | Same as indexed, no offset but increments the content of the H:X register after the instruction is executed. (4) | CBEQ X+, BRANCHLOC |
| 16-bit Indexed, 8-bit Offset with Post Increment (IX1+) | No | Yes | Same as indexed, no offset with post increment but with an 8-bit unsigned offset contained in the byte following the opcode. | CBEQ #OS8B, X+, BRANCHLOC |
| Stack Pointer, 8-bit Offset (SP1) | No | Yes | Similar to the indexed, 8-bit offset but the offset is added to the content of the stack pointer, rather than the index register, to form the reference address. (5) | LDA #OS8B, SP |
| Stack Pointer, 16-bit Offset (SP2) | No | Yes | Same as stack pointer, 8-bit offset but with a 16-bit unsigned offset contained in the two bytes following the opcode. | STA #OS16B, SP |
| Memory to Memory, Immediate to Direct (IMD) | No | Yes | Stores the immediate value following the opcode to the direct address specified by the third byte. (6) | MOV #$FF, $01 |
| Memory to Memory, Direct to Direct (DD) | No | Yes | Stores the data referenced by the direct address specified by the second byte to the direct address specified by the third byte. | MOV $01, $03 |
| Memory to Memory, 16-bit Indexed to Direct with Post Increment (IX+D) | No | Yes | Stores the data referenced by the address stored in the index (H:X) register to the direct address specified in the second byte of the instruction. The index register is incremented after the store takes place. | MOV X+, $1A |
| Memory to Memory, Direct to 16-bit Indexed with Post Increment (DIX+) | No | Yes | Stores the data referenced by the direct address specified by the second byte of the instruction to the 16-bit address stored in the index register. The index register is incremented after the store takes place. | MOV $50, X+ |
(1) Exceptions are the HC08's DBNZA and DBNZX instructions
which both require a relative branch destination following the
opcode. These instructions are actually combinations of inherent
and relative addressing modes, but they are classified as inherent.
(2) Exceptions are the HC08's CPHX, LDHX and STHX instructions
whose single-byte operand is the page 0 address of the most significant
byte of a 16-bit value. The data found at this MSB will be compared
to, loaded into or stored from the H register, respectively, while
the least significant byte, located in the next address and implicit
in the instruction, is compared to, loaded into or stored from
the X register, respectively.
(3) The BRSET and BRCLR instructions contain two operands,
the first being the location of the data in which the bit tested
is found, and the second operand being the relative address to
branch to if the condition is true. Note that there are 8 versions
of each of these commands, to correspond to the 8 possible bits
that can be tested.
(4) Post increment modes (IX+ and IX1+) are supported
by only one base instruction, CBEQ. The MOV instruction also
has post increment variations, but these instructions are classified
as different addressing modes.
(5) All stack pointer relative instructions require
a pre-byte ($9E) and therefore take one more byte than their index
relative counterpart.
(6) All four memory to memory modes are supported by
only one base instruction, MOV, and this base instruction doesn't
support any other addressing modes.