Figure 1 - Human Body Model (HBM) stressing.
EMC stands for electromagnetic compatibility. EMC problems occur in one of two categories: emissions or susceptibility. An MCU design that is affected by external noise sources has a susceptibility problem. An MCU design that is a noise source that affects other circuits is an emissions problem. View application note AN1259, System Design and Layout Techniques for Noise Reduction in MCU-Based Systems and application note AN1263/D, Designing for EMC Compatibility with Single-Chip MCUs for more information. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 EMI, EMC, ESD What is ESD?
Electrostatic discharge is the application of a short-duration, high-energy pulse to the external leads of an integrated circuit. ESD is often confused with electrical overstress (EOS). While both ESD and EOS failures are the direct result of localized heating, the location of the damage differs. Damage seen on bond wires and die metalization are typically associated with EOS, while junction degradation, contact damage, and gate oxide breaches are more often linked with ESD events. The reason for this difference in failure mechanisms is the rise time and duration of the energy pulse. While ESD events may only take less than a microsecond to happen, EOS events are much slower to occur and typically last much longer.
An electrostatic discharge happens when two objects at different potentials come in contact with one another. Charge is transferred from one body to the other until they are both at the same potential. The time required for this charge transfer to take place can vary and depends on the characteristics of the charged bodies, such as their capacitance and the resistance of the discharge path between them. This charge transfer is referred to as an ESD event. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 EMI, EMC, ESD How can objects build up an electrostatic charge?
Objects charge in a number of ways. Perhaps the most common is through frictional charging, also known as triboelectric charging. This involves the transfer of electrons from one object to another through direct contact. Several factors can affect the efficiency of the charge separation, such as relative humidity. For example, walking across a carpet in summertime when it's humid will not generate much charge, but could develop a signficant charge in wintertime, when humidty is low. The components in your television are in close proximity to the electric field generated by the picture tube. When the TV is switched off, there is a great deal of static electricity on the screen and case. Cracking and popping is also heard. This is the discharge of the field-induced charge that has built up on the various components inside the TV. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 EMI, EMC, ESD How are Motorola MCUs characterized with respect to ESD susceptibility?
To characterize devices, it is necessary to subject them to stresses that are repeatable and predictable. This has resulted in the development of three ESD models used to approximate real world ESD events. The first two deal with a charged body discharging to or through an IC to ground, while the third simulates a charged IC discharging to ground.
The Human Body Model (HBM) is used to approximate what happens when a person, charged up to some potential, discharges to or through an IC to ground. In this case, the human body has been modeled as a capacitor of 100 pF, discharging through a series resistance of 1.5 K-Ohms. The real-world situation and the model are depicted in Figure 1. When this capacitor is charged to 2000 V, it can deliver a peak current of 1.33 A to the device under test! This peak occurs only ~10 nsec after the event began!
Figure 1 - Human Body Model (HBM) stressing.
The Charged Device Model (CDM) is very different from both HBM and MM. In this case, the device itself is charged up and discharges to ground. For instance, a device sliding out of a plastic rail will charge up via triboelectric charging if the rail isn't treated with an anti-static coating. An IC has much less capacitance than a human body, typically only a few pF, and only a small amount of charge is needed to increase the potential on a device to several hundred volts (V = Q/C). Any charge built up on the device discharges very quickly because of this small capacitance, as is shown in Figure 2.
Figure 2 - Charged Device Model (CDM) stressing
Usually, a device which has failed to withstand an ESD event will have leaky or shorted pins. Because the stress enters the device through the pad, it stands to reason that the circuitry in closest proximity to this stress will fail first. Figure 3 shows a typical I/O pad configuration, and the curve traces for various types of pin failure modes. It is important to note that the four main failure mechanisms (discussed in the next FAQ) can cause any of these failure modes. Occasionally, high supply current and even functional failures can be seen on ESD failures.
Figure 3 - Schematic of a typical I/O pin and the curve traces of various failure modes
As mentioned earlier, four main failure mechanisms are associated with ESD events. They are junction degradation, thermal oxide degradation, poly melt filaments and contact damage. All are the direct result of localized heating caused by excessive current. It is important to understand the configuration of the output buffers, and their role in the ESD event. Figure 4 shows a cross section through an I/O pad and output buffers.
Figure 4 - Diagram of a cross-section through an I/O pad, showing output buffers
The high energy pulse which is absorbed by a pin travels through the pn junctions attached to the pad, which are the drains of the output n-channel and p-channel transistors for that pin. As is typical in an ESD event, the voltage applied to the pad exceeds the reverse bias breakdown voltage of the drain junctions. Impact ionization causes high current to flow through the diode. The current (and heat generated) eventually becomes localized due to some non-uniformity in the junction processing or the device lay out (i.e. the contact closest to the energy source). This increase in temperature increases the intrinsic carrier concentration, lowering the resistance along that current path. This becomes a preferential current site. More current flows here, generating more heat, lowering the intrinsic concentration, reducing the resistance, allowing more current to flow, and so on, a positive feedback system.
Contact damage, also called contact spiking, is the result of this particular phenomena. See Figure 5. When the excessive current causes the aluminum to heat beyond its melting point of 660 degrees C, the aluminum, which is positively charged, drifts into the substrate under the influence of the electric field. Eventually, the aluminum dopant reaches through the drain diffusion and into the substrate, shorting the drain/substrate diode and resulting in a pad- VSS leakage path.
Junction damage can also occur in this scenario. If the heat generated by this localized current flow exceeds the melting point of silicon (1400 degrees C), the silicon will melt and reflow, disrupting the dopant profiles in this region of the pn junction. When the ESD event is over, the silicon recrystallizes, with the n- and p-type dopants mixed up, resulting in poor isolation between p- and n- type regions and a leaky drain/substrate diode. This type of damage is visible only after a decoration etch is performed to highlight areas of damaged silicon. This failure mechanism is usually accompanied by other more visible mechanisms, such as contact spiking.
Figure 5 - Diagram of contact spiking
As mentioned earlier, more than one failure mechanism can be present on an ESD failure. The SEM micrograph in Figure 7 shows several mechanisms which occurred as the result of a single ESD event. The unit in this case has been stripped back to silicon. A spiked contact, poly melt filament "trench" and gate oxide rupture are all present.
Figure 6 - SEM micrograph of poly melt filaments. The unit has been stripped back to reveal polysilicon.
Figure 7 - SEM micrograph showing three ESD failure mechanisms resulting from a single ESD stress. A spiked contact, poly melt trench and gate oxide short are all present.
Electrical overstress (EOS) is the misapplication of excessive voltage or current to the external leads of an integrated circuit. The damage caused by EOS is actually a result of the total energy applied to the device. Externally, the damage will result in open, short or leaking pins. It can also affect the devices functionality. Internally, the result is typically seen as fused bond wires or damage to the die metalization. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 EMI, EMC, ESD What is the difference between EOS and ESD?
The key difference between EOS and electrostatic discharge (ESD) is the rise time of the energy pulse. Rise times associated with an ESD event are in the 5-20 ns range while the rise times for EOS events tend to be much longer. Failure mechanisms associated with both types of events are strictly due to localized heating. Where the localized heating occurs is key to understanding the failure mechanisms. Damage seen on bond wires and die metalization are typically associated with EOS (slow rise time, high energy) while junction degradation, poly melt filaments, and contact damage are associated with ESD (fast rise time, high energy). Typically, most ESD damage is visible only through deprocessing and SEM inspection. Most EOS damage is visible through an optical microscope. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 EMI, EMC, ESD Typical Failure Modes for EOS
The most common failure modes indicating an EOS event are open pins, shorted pins, and leaking pins. Figure 1 shows the curve traces for each of these situations on a standard I/O pin. Open pins are the result of bond wires or die metalization which has been vaporized and has fused open. Shorted and resistive pins are usually due to die metalization and oxide melting then reflowing into adjacent metal. Leaky pins can also be due to the reflowing of metal and oxide in and near active areas.
Figure 1. Schematic for a typical I/O pin and the curve traces which could be associated with the pin
The physical failure mechanism which results from an EOS event is greatly dependent on the total energy applied to the pin. Both time and current play roles in determining the total energy. Temperature also can be a factor since it is the act of melting metal and oxide which results in an EOS failure.
Only two failure mechanisms normally are associated with EOS: fused bond wires and fuse die metalization (Figures 2 and 3). The average bond wire for a 68HC05 device is 1 ml in diameter and approximately 60 mils long. A direct current of 1 Amp would be sufficient to fuse a bond wire of this dimension. Higher current pulses of shorter duration also could fuse a bond wire. For example, a 5 Amp, 1 msec pulse would most likely fuse the average bond wire. In both these cases, the energy dissipated is equivalent to the energy absorbed by the bond wire. Simple calculations show that when the temperature necessary to absorb this energy exceeds the melting temperature of the gold bond wire, the wire will fuse.
The second mechanism associated with an EOS event is fusing of die metalization. Typically, these events are extremely high current spikes of short duration (<170 usec). In this event, the heat dissipated on the die is conducted away from metalization through the SiO2 to the substrate. SiO2 is a fairly good thermal conductor. Therefore, the current needed to fuse the die metalization is fairly high, typically around 10 Amps.
Since heat plays a big part in creating the EOS damage, it is important to note that in plastic encapsulated devices, the actual fused metalization may not be visible due to carbonized plastic residue left on the die. This carbonized plastic is the direct result of the locally absorbed energy and its resulting high temperature.
Figure 2. SEM micrograph of a fused bond wire
Figure 3. Optical micrograph of typical EOS damage. Both fused and reflowed metal are evident.
The 68HC705C8A has two COPs (computer operating properly), a programmable COP and a non-programmable COP.
The programmable COP is provided for compatibility with the 68HC705C8. This COP has four different programmable timeout periods, selected by the CM1 and CM0 bits in the Programmable COP Control Register (COPCR, location $001E). The programmable COP is enabled by setting the PCOPE bit in the COPCR. This bit can be set through software once during operation, and it needs to be set again after every hardware reset. The COP counter is reset by writing the values $55 and $AA (in that order) to the COP Reset Register (COPRST, location $001D).
The non-programmable COP is provided for compatibility with the 68HC05C4A. Its timeout period is fixed (262,144/ FOSC). The non-programmable COP is enabled by setting the NCOPE bit in Mask Option Register 2 (MOR2, location $1FF1). This is an EPROM register, so the value for this bit is permanently programmed. The non-programmable COP counter is reset by writing a logic 0 to bit 0 of address $1FF0.
NOTE: Because the address $1FF0 is not in the first page of memory, the BCLR instruction cannot be used to reset the non-programmable COP. This instruction only works with the direct addressing mode. Use the sequence CLRA, STA $1FF0 to reset this COP.
NOTE: When using the 68HC705C8A, it is possible to have both COPs enabled. If the NCOPE and PCOPE bits are set, then both COPs will be enabled. Both COP counters will need to be reset at the appropriate times. This situation should be avoided. 1999Mar04 68HC05X32, 68HC705X32, 68HC05X16, 68HC705X16, 68HC05X4, 68HC705X4 Timer, Exceptions What are the 68HC05 "X" Family COP differences?
These devices all contain the MCAN module. However, the 68HC705X4 is radically different from the 68HC705X16 and 68HC705X32. The 68HC705X16 and 68HC705X32 are directly derived from the 68HC05B Family while the 68HC705X4 has the more recent core design which always contains the core timer. This has resulted in a very different operation of the COP between these devices.
The 68HC705X4 COP must be cleared by writing a '0' to bit 0 of address $1FF0 using the STA $1FF0 instruction while the 68HC705X16 and 68HC705X32 require a write of '1' to bit 0 of address $000C (the Miscellaneous register). Since the 68HC705X16 and 68HC705X32 have the COP refresh register in page zero it is possible to use BSET 0,$0C.
The COP time-out for the 68HC705X16 and 68HC705X32 is fixed at 4 mS (for 2 MHz bus) while the 68HC705X4 has a choice of approximately 50 mS up to 420 mS for a 2 MHz bus.
Note the different addresses of the MOR for the 68HC705X32 and 68HC705X16.
68HC705X16 MOR address $3DFE
68HC705X32 MOR address $7FDE. 1999Mar04 68HC705KJ1, 68HC05 Misc. What is the part number for a high speed version of the 68HC705KJ1?
No special part number is required for high-speed 68HC705KJ1 operation. The standard 68HC705KJ1 is specified to operate at the 4 Mhz internal bus speed (500 ns minimum instruction cycle) of other Motorola high-speed OTP versions (68HSC705xx). 1999Mar04 68HC705KJ1, 68HC05 Clocking What is the part number for a low-power 32 Khz version of the 68HC705KJ1?
The low-power 32 Khz oscillator version of the 68HC705KJ1 is 68HLC705KJ1. 1999Mar04 68HC05, 68HC05F6, 68HC705F6 CPU, Instructions How do the BIH and BIL instructions work with the 68HC05F6?
The 68HC05F6 has two external IRQ pins. The BIH and BIL instructions test the state of the IRQ1 pin only and not the IRQ2 pin! 1999Mar04 68HC05, 68HC08 Development tools Why do I need to apply the programming voltage if I just want to verify the contents of EPROM/OTP?
The MCU must be put into boot-load mode to program or verify OTP/EPROM parts on Motorola's parallel programmers. This is done by applying VPP to the board. Again, this is necessary even if just verifying the MCU contents. 1999Mar04 68HC05, 68HC08 Development tools Can I use the DB, FCB, DW, or FDB Pseudo-Ops to reserve RAM space with the IASM or CASM assembler?
Do not use the DB, FCB, DW, or FDB pseudo-ops to reserve RAM space since they can corrupt the portion of the bootloader that is copied into RAM.
When reserving space for variables in RAM, use the DS or RMB pseudo-ops. These pseudo-ops reserve bytes by changing the location counter in the assembler only. They do not actually write to the S-record when assembling.
When initializing ROM or EPROM, use the DB or FCB Pseudo-Ops for eight bits and DW or FDB pseudo-ops for 16 bits.
1999Mar04 68HC05, 68HC08 Memories, Development tools What are the most common types of programming problems encountered with OTP/EPROM MCUs?
The notes for the PLL frequency selection of 4.194 MHz state that this selection is for high-speed MCUs only. This device is not offered as a high-speed part. Therefore, this option should never be selected. A high-speed option is available for the ROM device (MC68HSC05E1). 1999Mar04 68HC705L5, 68HC05 Clocking Can you explain the 68HC705L5 MISC Register?
The two oscillators on the 68HC705L5 are called OSC and XOSC. OSC is the main oscillator and XOSC is the secondary oscillator. Several methods of clock distribution can be used for the 68HC705L5. The Miscellaneous Register (MR) is used to administer the system clock. It provides the following functions.
For easy reference the MR register is shown here.
Because the system clock can be changed through software, flags must be used to alert when a clock is stable, shut down, or powering up. The FTUP and STUP bits report these situations as they occur.
The FTUP bit is a read-only flag showing the status of OSC. 1 = OSC is stable and is available for the system clock. 0 = OSC is in the midst of a power-on reset and it has been disabled by the FOSCE bit (0), or the chip is in STOP mode.
The STUP bit is a read-only flag showing the status of XOSC. 1 = XOSC is stable and available for the system clock. 0 = XOSC is not stabilized or there is no connection on the XOSC1 and XOSC2 pins.
The SYS1 and SYS0 bits are read/write pins able to select one of four system clock sources. Refer to Table 6-1 on page 6-6 in the 68HC705L5 Technical Databook.
The FOSCE bit is a read/write bit that can turn the OSC on or off. 1 = This enables the OSC circuit to start running. After 8072 clocks, an overflow from the POR (power on reset) counter sets the FTUP bit. The OSC is now stable and available to be the system clock. 0 = When OSC is turned off, the FTUP bit is cleared and the POR counter is cleared. The 7-bit prescaler is also cleared. Do not clear this bit when OSC is the system clock.
WARNING:
When writing to the MR register, the chip will get locked up if you change the system clock to XOSC and turn off OSC with the same instruction. For example:
LDA #$0C
STA $3E ;chip will lock up
The proper way to change to XOSC and turn off OSC is:
LDA #$0E
STA $3E ;XOSC is system clock, OSC still running
LDA #$0C
STA $3E ;turn off OSC, FOSCE=0 1999Mar04
68HC05, 68HC705L5, 68HC05L5, 68HC705L16, 68HC05L16 Clocking How can I keep the LCD display refreshed on the 68HC(7)05L5/L16 when using STOP mode?
The 68HC05L5 has two oscillators: a standard OSC using up to approximately 4 MHz and a slower 32 kHz XOSC. During the STOP Mode, the XOSC does not stop oscillating. It can be used to drive the time base for the LCD driver. Therefore, during STOP Mode when the device is in low-power mode, the LCD driver will still operate keeping the display refreshed and overcoming the problem of the display clearing when STOP is entered.
The XOSC is selected by clearing the TBCLK bit in the TBCR1 register. This bit can be written to only once after reset in the ROM. This is not true for the EPROM part. 1999Mar04 68HC05, 68HC705L1, 68HC05L1 Clocking How can the 68HC(7)05L1's OSC still run in STOP mode?
Page 2-7 of the Product Preview (Rev 2.0) of the 68HC05L1/705L1 explains the Control Registers of the 68HC05L1. Control Register, CR1, at address $0A contains bit 4, the DON bit.
DON, bit 4 ---------- 0 = Turn off LCD 1 = Turn on LCD
The one exception when the OSC will still be running in STOP mode is when the LCD is not turned off before going into STOP mode. Make sure to turn off the LCD by clearing bit 4 of CR1 if you want the OSC to be off in STOP mode. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Clocking Can I use an external oscillator to drive the 68HC908GP20/32?
Yes. An external canned oscillator or square wave can be used to drive the 68HC908GP20, up to a maximum frequency of 32 MHz externally, with the PLL off. With the PLL on, an external clock can be used up to 1.5 MHz external speed. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Clocking If I use a high-frequency external clock source, can I still use the 68HC908GP20/32 PLL?
The PLL is designed for use with a 16 kHz to 100 kHz reference signal, optimally with a 32 kHz crystal. If you use the PLL, the absolute highest value crystal is limited to 100 kHz.
Using an external (canned, square wave) oscillator, the fastest speed that can be used with the PLL is limited to 1.5 MHz. In the case of up to 1.5 MHz, the divider value R in the PLL control registers is used to divide down the crystal frequency to a reference frequency that falls within the 16 kHz to 100 kHz range. If an external clock higher than 1.5 MHz were used, the R value could not be high enough to reduce the reference signal to less than 100 kHz. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Clocking What is the fastest crystal I can use on the 68HC908GP20/32? Can I use a 16 MHz or other high frequency crystal with the 68HC908GP20/32?
The crystal option 68HC908GP20 is only designed to work with a 32 kHz to 100 kHz crystal. Faster crystals should not be used. If the crystal option is selected, the user must connect a 32 kHz to 100 kHz crystal and use the PLL to generate desired bus speeds up to 8 MHz. 1999Mar04 68HC05, 68HC705J1A, 68HC05J1A Clocking Can I use the 68HC705J1A below 2 MHz?
The J1A is a fully static part which can operate with an internal bus speed from DC to 2 MHz. When trying to save power, it is recommended that you operate at the lowest possible frequency and use STOP mode as much as possible. When using an external crystal, use an AT-cut parallel resonant crystal. 1999Mar04 68HC05, 68HC705J1A, 68HC05J1A Clocking What is the short oscillator delay option and how do I select it on the 68HC705J1A?
The short oscillator delay is selected by setting the SOSCD bit in the MOR (bit 7, location $07F1). This is an EPROM register, so once programmed, it is permanently set.
The normal oscillator delay following reset or exit from stop mode is 4064*tcyc. When the short oscillator delay is enabled, the delay becomes 128*tcyc.
NOTE: The short delay period depends on the mask set of the device. For mask set F44T, the delay is 16*tcyc. For mask sets G58F and G63P, the delay is 128*tcyc.
1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 Timer What is the input capture function and how is it used?
Using the input capture function, an input signal is used to trigger a read of the free-running counter. When an external event is detected on the TCAP pin, the value of the timer counter is saved in the input capture register. In this way, the relative time the event occurred is recorded.
One use of input capture is to measure the period or the pulse width of a signal. By capturing the time of two successive edges of the same polarity, the time elapsed between periods can be determined. By capturing two alternate polarity edges, the width of a pulse can be determined. In either case, one could find the difference of the input capture registers at the time of the two events and use this difference to find the time elapsed between events (counter difference divided by the timer frequency).
The input capture function can be interrupt driven or can be polled using the input capture flag (ICF).
" 1999Mar04
68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 Timer What is the output compare function and how is it used?
The output compare function allows an action to occur at a specific time. When the value programmed into the output compare register matches the value of the timer counter, a predefined output is generated on the TCMP pin (for 68HC05 MCUs) or other output pin.
One use of the output compare function is to produce a pulse of a specific duration. By controlling the OLVL (Output Level) bit and the value of the output compare register, the signal at the TCMP pin (or other pin) can be pulse-width (or pulse-length) modulated.
Another use of the output compare function is to generate a specific delay. In this case, one doesn't particularly care to generate an external signal, but use the timer as a programmable alarm clock. By using the output compare interrupt, one can set the timer for a particular value and continue processing. When the value in the output compare register matches the free-running timer, an interrupt is generated and the timer code can take over.
Output compare delays can also be used to generate edges that trigger or synchronize external events. In this case, the edge polarity is the controlling signal instead of the pulse length.
The output compare function can be interrupt driven or can be polled using the output compare flag (OCF).
1999Mar04
68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 Timer What is a PWM (pulse-width-modulated) signal?
A PWM signal is a signal with a fixed frequency and variable on and off times. In other words, the period of the signal remains constant, but the amount of time that the signal remains high and low can vary within a period. Such a signal can be generated by using the output compare function of the timer subsystem.
The duty cycle (DC) of a PWM signal is the ratio of on time to the total period (on time + off time). Such signals are useful to control devices or provide a variable DC voltage. Common applications include motor, lighting, and climate controls.
For more information, useful PWM resources are:
application note AN1734/D, Pulse Width Modulation Using the 16-Bit Timer
TIM08RM/AD, M68HC08 TIM08 Timer Interface Module Reference Module 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300 Timer How can I use the timer subsystem to produce pulse-width-modulated (PWM) signals?
There are several ways to produce PWM signals with Motorola MCUs. Some parts have dedicated PWM circuitry. For example, the (7)05B16 has two PWM channels directly linked to its timer subsystem.
The most convenient method to implement involves the use of the output compare function. Given a desired duty cycle and frequency, one can determine the amount of timer counts necessary to produce the on and off segments that compose a pulse train.
These timer delays can be added to the current timer counter value and stored in the output compare registers. The value of the OLVL (output level) bit in the timer control register determines the logic level which will be output to the TCMP pin on the next valid compare.
Through the OLVL bit, the TCMP pin output level for the next valid compare can be set. When the timer counter reaches the value in the output compare registers, the OLVL bit value is asserted on the TCMP pin, and an interrupt can be triggered. The interrupt can then setup the next output level and delay. In this fashion, a pulse train of varying logic levels and durations can be output through the TCMP pin.
This method is documented in application note AN1734D, Pulse Width Modulation Using the 16-bit Timer. 1999Mar04 68HC05, 68HC08 Timer What are the timer registers and the alternate timer registers and how do I use them?
Both the timer registers and the alternate timer registers contain the current high and low bytes of the 16-bit counter. In most parts, these are read-only registers.
Reading the high byte of either the timer registers or the alternate timer registers will return the high byte of the counter and latch the value of the low byte into a buffer. Reading the low byte will return the value in the buffer, completing the read sequence. The value latched in the buffer will remain fixed, even if the high byte is read more than once before the low byte is read.
The difference between the two is that a read of the timer register low byte after reading the timer status register clears the timer overflow flag (TOF) bit. Reading the alternate timer register does not affect the TOF bit.
NOTE: The alternate register should be used to read the timer counter in all cases except when intending to clear TOF. This will avoid the possibility of the TOF being cleared unintentionally. 1999Mar04 68HC05, 68HC08 Timer Can the timer counter be reset through software?
In most 68HC05 MCUs, the free-running counter can't be reset. One exception is the 68HC(7)05B16. In this MCU, a write to the timer registers causes the counter to be reset to a known value. Consult the appropriate data book for details.
The 68HC08 Family of MCUs does allow the counter timer to be reset.
A reset (external, internal, or power-on) always sets the timer counter to a known value, typically $0000 or $FFFC. 1999Mar04 68HC05, 68HC08, 68HC11 Timer What is a real-time interrupt (RTI)?
The real-time interrupt is a feature of some Motorola MCUs. It allows an interrupt to be generated at a constant interval. For example, the 68HC705J1A offers four programmable real-time interrupt rates.
The real-time interrupt feature is useful for implementing tasks which occur on a regular, periodic basis. Examples include checking for external events, periodic waking from a low power mode, running periodic maintenance tasks, etc.
The advantage of a real-time interrupt is that it doesn't require as much software overhead as the output compare function. The disadvantage is that it is not as flexible, offering a limited number of periods. 1999Mar04 68HC05, 68HC08 Timer How do I use the timer control and status registers (TCSR)?
The timer control register (TCR) allows the user to control the timer subsystem functions. One important function of the TCR is to enable and disable interrupts generated by the timer subsystem. There is typically a bit for each of the timer interrupt sources (input capture, output compare, timer overflow, and real-time interrupt) which enables or disables its respective interrupt.
The TCR usually contains a bit (IEDG) which defines the active edge polarity of the TCAP signal for an input capture function. There is also a bit (OLVL) to define the logic level for output to the TCMP pin on a valid output compare.
The timer status register (TSR) contains flag bits, indicating the occurrence of the timer events (output compare, input capture, timer overflow, and real-time interrupt). Each flag drives its respective interrupt, if enabled. If the interrupt is not enabled, the flag still gets set and can be polled if desired. These flags can also be used to determine the source of a timer interrupt.
These flags should be cleared as the timer events are serviced. It is important to properly clear the flags, so the interrupt logic does not acknowledge duplicate interrupts. This is typically done by:
Some parts, such as the 68HC705J1A, have a combined timer control and status register, and flags are cleared by writing to a flag reset bit in the register. For details on a particular part, consult the appropriate data book. 1999Mar04 68HC05, 68HC08 Timer What are the programming gotchas for the timer subsystem?
The most important issue when programming the timer subsystem is code latency. The amount of time it takes to execute timer routines will determine the speed at which the timer subsystem can be used.
Example: producing a square wave signal using the interrupt-driven output compare function of the 68HC705C8A, running at an internal frequency of 2 MHz. At this bus frequency, the timer subsystem has a frequency of 500 kHz and a period of 2 us. Assume the routine which services the output compare interrupt takes 50 cycles (including the overhead of entering the interrupt) or 25 us. Because the code to set up an output compare pulse takes 25 us, this is the minimum pulse length that can be produced. This would limit the square wave output to a maximum attainable frequency of 20 kHz at a standard bus frequency of 2 MHz.
High-speed parts like the 68HSC705C8A, which provides a 4 MHz bus speed, can achieve even higher PWM frequencies. Using the example here, the 68HSC705C8A could achieve a square wave frequency of 40 kHz.
Another important programming consideration is the use of flags in the status register. In an interrupt-driven scheme, the interrupt sources of the timer subsystem share the same interrupt vector. Because of this, the interrupt service routine must determine which timer function caused the interrupt. This can be done through testing of the flags in the status register.
Once a timer interrupt is serviced, it is important to clear its flag in the status register. If the flag is not cleared after servicing the interrupt, then immediately after the return-from-interrupt (RTI) instruction, the same event will cause a duplicate interrupt.
For The 68HC08 Family Timer:
Programmers who use the TIM08 for PWM generation should note the following about the Timer Modulo Register. The Timer counts 0000 and the number in the Modulo Register as the timer ticks. Therefore, the frequency output from the timer channel is:
input / [prescaler * (modulo +1)]
Note the 1 added to the modulo value due to counting both 0000 and the modulo value.
The extra cycle is only .0015% of a period for a modulo value of $FFFF so it is below most measurement error. However, it becomes significant at lower modulo values. It is 3.1% of a period for a modulo value of $0020. 1999Mar04 68HC05, 68HC08 Timer What are the timer capabilities of common MCUs?
Listed here are popular Motorola MCUs and their available timer functions.
68HC05 Timer Features
| 705B16 | |||||
| 705C8A | |||||
| 705C9A | |||||
| 705JJ7 | |||||
| 705JP7 | |||||
| 705J1A | |||||
| 705KJ1 | |||||
| 805K3 | |||||
| 705L16* | |||||
| 705P6A |
The timer overflow function lets the user know when the timer counter has rolled over. This function is useful for extending the range of the timer subsystem.
For example, in the 68HC705C8A MCU, the timer counter has a range of 16 bits. This allows a resolution of 2us at an internal frequency of 2 MHz.
Timer frequency = 2 MHz/4 = 500 kHzTimer period = 1/500 kHz = 2us
Timer overflow period = 2 us * 65,535 = 131 ms
If the number of timer overflows are counted through software, the range is extended at a resolution of 131 ms.
The timer overflow event can trigger an interrupt, or can be polled using the timer overflow flag (TOF). 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 Timer, Exceptions How do I reliably use a COP (computer operating properly) watchdog timer?
The primary purpose of an MCU COP is to momentarily RESET the MCU when the MCU device is out of control: for example, in the case of software runaway. The MCU then will come out of RESET and will once again operate in a controlled manner.
The MCU COP is implemented in silicon as either a timer or a counter. The clock source driving the COP can be derived from the MCU bus clock or in some cases an on-chip RC oscillator. When the COP timer, or counter, reaches a predetermined value it generates a signal which will RESET the device - this value determines the COP TIMEOUT PERIOD. The minimum value of this period can be found in the device data book and will be quoted in terms of bus clock cycles or in terms of time versus bus frequency.
To prevent the COP from reaching its final value and therefore from RESETING the MCU, it must be REFRESHED. This operation must occur within the minimum COP TIMEOUT PERIOD. The method of refreshing the COP depends heavily on the COP implementation.
In the case of 68HC05 devices which have the MFT, or CORE TIMER, the general method is to write '0' to bit 0 of an address specified in the device data book. This will normally require a LOAD and STORE instruction (BSET/BCLR instructions cannot be used when the refresh address is out side page 0 memory i.e. out side the range $0000 - $00FF).
In most other 68HC05s, the COP is refreshed by storing the values $55 then $AA into the COPRST register. Some 68HC05s also have a CLOCK MONITOR RESET feature which will RESET the device if the device clock source is lost; for example, if the clock oscillator crystal was to become disconnected from the device.
When refreshing the COP, the following points should be considered:
In some cases, multiple refresh instructions throughout the code are unavoidable. For example, where there is a possibility that the refresh may not occur within the time-out period even when the code is executing correctly. They should, however, be kept to a minimum. The reason for having one instruction, or section of code, to refresh the COP is that if the software runs away, it may find itself caught in a loop of code, a section of which refreshes the COP. If this happens the COP is being refreshed and the code is not executing correctly. The device will not RESET in this case.
No. When the SIOP is enabled by setting the Serial Port Enable (SPE) bit of SCR high, the data direction register automatically is configured to set SCK as an output in master mode or as an input in slave mode, SDI as an input, and SDO as an output. If the SIOP is later disabled by clearing SPE, then the port DDR will revert to whatever it was previously set to. 1999Mar04 68HC05 Serial Communication What is the bit transmission order for the SIOP?
The SIOP is configurable as a mask option to transmit the least or the most significant bit first. Normal configuration is most significant bit first. 1999Mar04 68HC05, 68HC08 Serial Communication Is the configuration of the data direction register (DDR) for the port that the SPI uses of any concern when using the SPI?
For the pins that are used as SPI inputs (MISO for a master and MOSI, /SS and SCK for a slave), the setting of the DDR is not important. The pins will be configured as inputs regardless of the DDR setting. For pins that are used as SPI outputs (MOSI and SCK for a master and MISO for a slave), the setting of the DDR is important and must be set to reflect these pins as outputs. 1999Mar04 68HC05, 68HC08 Serial Communication When should SCI address mark wake-up be used and when should idle line wake-up be used?
The wake-up feature of the SCI is enabled by setting the Receiver Wake-up (RWU) bit of the SCCR2. This will put the receiver to sleep, disabling receiver interrupts, until it is awakened by one of two ways. One wake-up method, address mark, which is implemented by setting the Wake-up Mode Select (WAKE) bit of the SCCR1, will cause the receiver to wake up when a byte of data is received which has a most significant bit of 1. The most significant bit will be bit 8 when 9-bit data mode is selected (M = 1), and bit 7 when 8-bit data mode is selected (M = 0). When this occurs, the hardware clears the RWU enabling interrupts, and the receiver would read the byte to see if it represents its own address and, if so, would process the message that follows. If the byte did not represent its address, then it would ignore the message as it own address and, if so, would process the message that follows. If the byte did not represent its address, then it would ignore the message as it is meant for another device and set the RWU bit once again.
The other wake-up method, idle line, which is implemented by clearing the WAKE bit, will cause the receiver to wake up whenever the line is idle, during which time 11 or 12 1's will appear on the receive line. This configuration requires that there be at least one character time of idle between messages to wake up sleeping receiver, but that there be no idle time between characters within a single message. Note that for both wake-up methods, the IDLE flag of the SCSR is disabled when the RWU bit is set which disables the idle interrupt
Using address mark wake-up requires a bit to be used to designate an address byte, which dictates the length of all other bytes of data. It relieves any concern about waking up receivers when there may be frequent idle states. This method would be favorable when specific receiver-directed messages rather than broadcasts are used extensively, especially if the messages are long (where reading an entire message intended for another receiver is prohibitive and where the address bit does not cause a serious overhead in the transmitted data. This would be so if the address range goes no higher than 127 and bit 7 could be used as the address bit, rather than having to make the character length nine bits to accommodate the address bit and at the same time causing all data to conform to the longer character length.
Idle wake-up is useful when an address bit would cause too much overhead on message lengths and where waking up because of idle time is of no concern or actually desirable. This configuration may be used when broadcasting data to multiple stations, and/or when there is frequent, almost continuous communication among stations on the link. In this scenario, a master can control the state of the receivers (whether they are in a dormant mode) by not allowing any idle time on the line. 1999Mar04 68HC05, 68HC08 Serial Communication For SCI interrupt-driven data transmission, which of the two transmit interrupts, Transmit or Transmission Complete, should be enabled to provide the lowest latency and fastest data throughput?
The Transmit interrupt, if enabled by having set the Transmit Interrupt Enable (TIE) bit, is triggered when the Transmit Data Register Empty (TDRE) bit becomes set. This occurs upon transfer of the data byte to the shift register. The shift register must then be emptied by shifting out each bit of the byte being transmitted. The Transmission Complete interrupt, if enabled by having set the Transmission Complete Interrupt Enable (TCIE) bit, is triggered when the Transmission Complete (TC) bit becomes set. This occurs only after the byte has been completely transferred out and the shift register is empty. It is therefore more efficient to cause a Transmit interrupt when the data register is empty so it can be loaded with the next byte of data while the shift register is transferring the prior byte. 1999Mar04 68HC05, 68HC08 Serial Communication What is the default (reset) state of the SCI status bits in the SCSR and how is each bit cleared?
The TDRE and the TC bits have a default value of 1 while the remaining bits of the SCSR (RDRF, IDLE, OR, NF, and FE) have a low default value. To clear the TDRE or the TC bits, first read the SCSR while the bit is set and then write to the SCDR. As soon as the data that was sent to the SCDR is transmitted, both of these bits will return to a high state. To clear one of the remaining bits, either cause a reset or first read the SCSR while the bit is set and then read the SCDR. 1999Mar04 68HC05, 68HC05C8A, 68HC705C8A, 68HC05C9A, 68HC705C9A Serial Communication What are the SPI differences between the 68HC(7)05C8A and 68HC(7)05C9A?
Although the HC(7)05C9A appears to have the same Serial Peripheral Interface as the C8A device , note should be taken of the slight variation in Port D operation to avoid problems with use. As can be seen from the C9A memory map, Port D Data Direction Register at $07 allows the user to configure the port lines as either input or output (fixed as inputs on other Cx devices). When using the SPI function, the contents of this register affect the operation of the SPI as it shares port D with the I/O lines. If using the device as an SPI, the direction of SPI data must be set in DDRD ($07) in the same fashion as Port lines. ie. Storing the value $18 in DDRD ($07) configures SS (bit 5) as input SCK (bit 4) as output MOSI (bit 3) as output MISO (bit 2) as input.
This configuration will give the correct operating conditions to use the HC(7)05C9A device as an SPI master in the same fashion as other 68HC05Cx devices. 1999Mar04 68HC05, 68HC705B16, 68HC05B16, 68HC705B32, 68HC05B32, 68HC05B6 Serial Communication How are the features of the SCI+ different from those of the SPI and the SCI?
The SCI+ (Serial Communications Interface +) system combines capabilities of both the synchronous SPI (Serial Peripheral Interface) and the asynchronous SCI. The SCI+ loses some of the functionality of the SPI but improves upon it with other features, while several of the features of the SCI are enhanced in the SCI+. Features of all three systems are contrasted in the table here.
Feature | SPI | SCI | SCI+ |
Transmission Type | Synchronous | Asynchronous | Synchronous/Asynchronous |
Baud Rate | 4 selectable rates; transmit rate = receive rate | 32 selectable rates; transmit rate = receive rate | 32 selectable rates; transmit and receive have same first prescaler stage (selectable 1 of 4), but have separate second prescaler stages (selectable 1 of 8); transmit rate does not have to equal receive rate |
Data Bits | 8 bits only | Selectable 8 or 9 bits | Selectable 8 or 9 bits |
Master Mode Selection | Allows appointment of a bus master to control communication to/from slave(s) | N/A* | N/A |
Port Enabling/ Wake-up Method | Enables receiving of data and the clock by a slave through the Slave Select (/SS) pin, pin also selects/deselects the master | TE and RE enables transmitting and receiving of data, respectively; Receiver Wake-up Enabled (RWU) bit enables wake-up method selected by WAKE bit; WAKE bit selects either address mark or idle line wake-up | TE and RE enables transmitting and receiving of data, respectively; Receiver Wake-up Enabled (RWU) bit enables wake-up method selected by WAKE bit; WAKE bit selects either address mark or idle line wake-up |
Transmission Flags | One flag for completion of either transmit and receive | Separate flags for Transmit Complete (TE), Transmit Data Register Empty (TDRE), Receive Data Register Full (RDRF) and Idle Line Detected (IDLE) | Separate flags for Transmit Complete (TE), Transmit Data Register Empty (TDRE), Receive Data Register Full (RDRF) and Idle Line Detected (IDLE) |
Error Flags | Write Collision (WCOL) and Mode Fault (MODF) | Overrun (OR), Noise (NF) and Framing (FE) | Overrun (OR), Noise (NF) and Framing (FE) |
Interrupts | Single interrupt (SPIE) may be asserted upon the transmitting or receiving of 8 bits of data | Transmit data register empty (TIE), transmission complete (TCIE), receive data register full or receiver overrun (RIE), idle line (ILIE) | Transmit data register empty (TIE), transmission complete (TCIE), receive data register full or receiver overrun (RIE), idle line (ILIE) |
Break Code Support | N/A | Send Break Code (SBK) bit enables continuous sending of break code | Send Break Code (SBK) bit enables continuous sending of break code |
Clock Polarity/ Phase Control | Clock Polarity (CPOL) bit selects polarity of line between transmissions; Clock Phase (CPHA) bit selects rising or falling edge of clock to latch synchronous data | N/A | Clock Polarity (CPOL) bit selects polarity of line between transmissions; Clock Phase (CPHA) bit selects rising or falling edge of clock to latch synchronous data |
Last Bit Clock | N/A | N/A | Last Bit Clock (LBCL) bit enables/disables clock signal on last (8th or 9th) bit transmitted |
*N/A = not available or not applicable
Note that the SCI+ nomenclature in the 68HC05 Family has different connotations from the meaning of SCI+ in the 68HC11 Family. In the 68HC11's, the SCI+ expands on the number of baud rates that can be selected by providing a 13-bit prescaler. Unlike the 68HC05's SCI+, it does not add support for synchronous serial communication. 1999Mar04 68HC05, 68HC05L5, 68HC705L5, 68HC05L16, 68HC705L17 Serial Communication How are the SPI and the SSPI in 68HC05s different?
As its name implies, the Simple Serial Peripheral Interface, or SSPI, is a simplified version of the Serial Peripheral Interface, or SPI. There are a few minor differences between the two systems. The user should be aware of:
The following table shows the functional differences between the two systems.
Function | Control/Status Bit | Supported in SPI? | Supported in SSPI? | Default State/Comments |
System Enable | SPE in the SPCR | Yes | Yes | Default is system disabled |
Interrupt Enable | SPIE in the SPCR | Yes | Yes | Default is interrupt disabled |
Master Mode Select | MSTR in the SPCR | Yes | Yes | Default is slave mode |
Data Transmission Order | DORD in the SPCR | No | Yes | Default order is MSB first |
Clock Polarity Bit | CPOL in the SPCR | Yes | No | Default is a low logic state for clock between transmissions for the SPI |
Clock Phase Bit | CPHA in the SPCR | Yes | No | Default is data transmission on falling edge of clock cycle; /SS must be toggled between byte transmissions in the SPI |
Clock Rate Bit(s) | SPR1 and SPR0 in the SPI, only SPR0 in the SSPI | Yes (2 bits) | Yes (1 bit) | Default for both systems is divide by 2; SSPI can also be set to divide by 16, while the SPI can also be set to divide by 4, 16 and 32 |
Serial Transfer Complete Flag | SPIF in the SPSR | Yes | Yes | Default is data transfer not complete |
Write/Data Collision | DCOL (for SSPI) or WCOL (for SPI)) in the SPSR | Yes | Yes | Default is no invalid write to the SPDR |
Mode Fault Bit | MODF in the SPSR | Yes | No | Default is /SS has not been pulled low while MSTR bit is set |
The 68HC05C4A is our lowest price MCU with hardware asynchronous serial communications (SCI). Software can be used with any 68HC05 to emulate the SCI in cost sensitive applications. Refer to application note AN1240/D, Software driven Asynchronous Serial Communication Techniques. 1999Mar04 68HC05 Serial Communication What are the differences between the SIOP and the 68HC05's SPI?
The SIOP is similar to the SPI in that they are both synchronous communication systems. They are, however, different is some important ways:
Some confusion exists as to what, if anything, must be written into the DDRD when using the SCI subsystem. With the SPI subsystem, the DDRD must be written to define certain pins as outputs and certain pins as inputs (see the SPI section). However, with the SCI this is not the case. When the SCI is enabled, the affected pins automatically configure themselves to the proper input or output state. The DDRD need not be written to. 1999Mar04 68HC05 Serial Communication In the 68HC05's SPI, how are the three status bits cleared in the SPSR?
The method of clearing the Mode Fault Flag (MODF) is different from the way the other two status bits of the SPSR, the Serial Transfer Complete Flag (SPIF), the Write Collision Flag (WCOL), are cleared. The following table explains the differences.
Flag | Clear Method |
Serial Transfer Complete Flag (SPIF) | Read the SPSR with SPIF set, then read from or write to the SPDR. |
Write Collision Flag (WCOL) | Read the SPSR with WCOL set, then read from or write to the SPDR. |
Mode Fault Flag (MODF) | Read the SPSR with MODF set, then write to the SPCR. |
No. To enable the SIOP, you must set the SPE bit in the SCR (SIOP Control Register, $000A). Port B data registers can still be written to. However, if you write to either port B register while a data transfer is occurring, you could corrupt the data that is being transferred. Also note that there are only three bits that may be used as I/Os (PB5:PB7). 1999Mar04 68HC05, 68HC705C9A, 68HC05C9A Serial Communication Does the SCI operate in full-duplex mode on the MC68HC705C9A?
The SCI has the option of allowing full-duplex communication. The SCI transmitter and receiver operate independently of one another, even though they are controlled through the same register. The SCI data register (SCDR) is controlled by the internal read/write signal. This means that when data is written to the register, it is a transmitter, and when data is read, it is a receiver. SCCR2 is the control register for the SCI. Selecting the RE or TE bit (bits 2 and 3 respectively) enables the receiver and/or transceiver. 1999Mar04 68HC05, 68HC08, 68HC11 Analog What happens when I use a resistor in series with an analog input pin?
Adding a series resistor to a pin can cause input leakage which would cause the A/D accuracy to degrade. Some users may want to include a series resistor to give some protection for operating below A/D voltage specifications. See the minimum voltage FAQ that follows for more information. 1999Mar04 68HC05, 68HC08 Analog What is the minimum voltage for the A/D input or reference pins?
If the input pin voltage is driven below VSS, it may cause a disruption in the A/D conversion process. Anything greater than a half diode drop (0.3 V) below VSS will cause permanent damage to the A/D input pins. This will also affect any adjacent analog pins. This is due to the diode connected to VSS. To help prevent damage, a series resistor may be added. A recommended value is R = 1 k ohms. Any value greater than 10 k ohms will cause input leakage leading to A/D accuracy being degraded. 1999Mar04 68HC05, 68HC08 Analog Why are there no collisions when the A/D is writing to the register at the same time the CPU is trying to read the register?
No collisions occur because the CPU accesses data on the falling edge of a clocked signal and the A/D accesses data on the rising edge of a clocked signal. 1999Mar04 68HC05, 68HC08 Analog What is the relationship amoung VREFL, VREFH (analog reference voltages) and VDDA, BSSA (analog supply pins)?
VREFH must be less than or equal to VDDA, while VREFL must be greater than or equal to BSSA. 1999Mar04 68HC05, 68HC08 Analog What voltage is needed between VREFL and between VREFH (analog reference voltages) for the best A/D conversion accuracy?
The voltage between VREFL and VREFH should be at least 2.5 V for A/D accuracy. Lower values will cause more inaccuracy for A/D conversions. The converter will still operate. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 Analog How can I improve the accuracy of A/D conversions?
When the A/D converter is enabled, pins PC3-PC6 become analog inputs. Any unused analog inputs may be used as digital inputs. However, they may not be used as digital output pins. Only pins PC0-PC2 can be used as digital output pins when the A/D converter is enabled 1999Mar04 68HC05, 68HC705C8A, 68HC05C8A Memories What do I have to consider when moving from the OTP 68HC705C8A to the mask ROM C8A?
EPROM and OTP devices are often supersets of mask ROM devices. Be sure to check both the mask ROM databook and the OTP data book when doing your design. Pay careful attention to mask option differences and the following:
The C8A/C9A has three areas of RAM: the 176-byte main block at $50-$FF and two smaller blocks which share memory map space with program memory (either EPROM in the 68HC705 or ROM in the 68HC05). These two smaller blocks, called RAM0 RAM and RAM1 RAM, are enabled by the RAM0 and RAM1 bits of the Option register. The default (reset) state of these bits is low, which disables these RAM blocks in favor of enabling program memory that is mapped in these ranges. 1999Mar04 68HC05, 68HC705C8A, 68HC05C8A, 68HC705C9A, 68HC05C9A Memories In the 68HC705C8A/C9A, is RAM content retained in RAM0 or RAM1 space when RAM0 or RAM1 is set to 0, thereby enabling program (ROM/EPROM/EEPROM) memory in that memory block?
The RAM0 and RAM1 bits of the Option register can be changed at any time during normal operation. When one of these RAM blocks is enabled and something written to one or more of its cells and then the block is disabled and later re-enabled, the RAM's content will be retained as long as power has not been interrupted. 1999Mar04 68HC08, 68HC11 Memories Can I take my existing application developed with an OTP/EPROM and submit a mask ROM with no changes?
EPROM and OTP devices are often supersets of mask ROM devices. Be sure to check both the mask ROM data book and the OTP data book when doing your design. Pay careful attention to mask option differences. For example, the following are two potential problem areas of the 68HC705C8A and 68HC05C8A if the user is not aware of these differences:
Margin read is a process which places a more stringent condition on the bit cell than what takes place during a normal read operation. This condition results in a more negative gate voltage being applied to the bit cell for a period of time that is eight cycles longer than during a normal read. Long-term data retention is assured when correct data is read under these conditions. This type of read is performed after each progressive program bump in the smart programming algorithm to see if the bytes in the page have been programmed adequately or whether the page needs to go through another program/read cycle. 1999Mar04 68HC08 Memories Is external high voltage required to program FLASH?
No. FLASH can be programmed with no external high voltage and with the device powered as low as 3.0 volts. Note, however, that block protection can be disabled only when there is high voltage ( VDD + 2.5 V) on IRQ and that this voltage is required to enter monitor mode when the device is not blank. This mode of operation is necessary when the device is blank, or it may be preferred for programming, depending on the method and tools selected for FLASH programming. 1999Mar04 68HC08, 68HC908GP20 Memories Is there anything special that I need to do to program/erase FLASH when VDD is 3.0 volts?
Yes. To enable the low-voltage mode of the FLASH charge pump, which is required whenever VDD is less than 3.6 volts, the FLASH Charge Pump Select Gate VOLtage Low- VOLtage Enable Bit (PMPSGVLVEN) in the CONFIG1 register needs to be set. To conserve power, this bit should be cleared when not programming at a VDD voltage lower than 3.6 volts. 1999Mar04 68HC08, 68HC908GP20 Memories What ranges of FLASH memory can I select to be protected and how do I unprotect it?
One of two ranges can be selected for block protection. The entire FLASH array can be protected by setting any, or any combination, of bits 0 - 2 of the block protection register. Setting bit 3 of this register, with bits 0 - 2 cleared, will select the range $C000-$FFFF for protection. In this latter protection setting, the range $B000-$BFFF is left unprotected and may be erased and reprogrammed without turning off block protection. Block protection can be disabled only when there is high voltage ( VDD + 2.5 V) on IRQ, and is done by erasing the range (row, 8-row block, array or full array) in which the block protection register ($FF80) resides. 1999Mar04 68HC08, 68HC908GP20 Memories How do I handle a page that I want to program when not all the bytes in the page are in the FLASH array, i.e., $FFD8-$FFDF?
The page program procedure as specified in the FLASH section of the 68HC908GP20 data book requires that a write is made to each address being programmed with the data intended to reside there. If a byte in the page to be programmed is not in the FLASH array, then omit the write to this location. You may also want to modify the normal page verification stage to not include checks for bytes out of the FLASH array to avoid erroneous verification failures. 1999Mar04 68HC08, 68HC908GP20 Memories What is the recommended method of programming and erasing the FLASH memory in the 68HC908GP20?
Programming the FLASH in the 68HC908GP20 is done on an 8-byte page basis and utilizes a smart programming algorithm of successive program and margin-read iterations. This algorithm, described and shown in flow chart form in the FLASH section of the 68HC908GP20 data book, guarantees that each byte in the page gets programmed adequately in as short a period of time as possible. This is done not only to minimize overall programming time, but also to maximize the life of the FLASH by reducing its exposure time to the programming voltage. All timing parameters referenced in this procedure and defined in section 25.19 (memory characteristics) should be adhered to as closely as possible.
The recommended method for erasing FLASH is non-iterative, as a single exposure to high voltage for the specified period of time (TERASE) is adequate for full erasure. The FLASH erase procedure is outlined in section 11.6 of the GRS. The size of the block of memory to be erased is specified by the block bits (BLK1 and BLK0) set in the FLASH Control Register (FLCR), and the address written to during the erase procedure determines the location of the block.
Note that for each of these operations, a charge pump frequency close to 2 MHz needs to be established. This is done by setting the FDIV bits in the FLCR. The charge pump frequency is derived as a binary division factor of the internal bus frequency. These bits need to be set appropriately for FLASH to be programmed or erased successfully.
Application note AN1770/D, In-circuit Programming of FLASH Memory in the MC68HC908GP20, describes FLASH programming in detail and can be used as an additional source of information on this topic. 1999Mar04 68HC05, 68HC705J1A Memories Can all of EPROM be programmed in user mode in the 68HC705J1A?
No. The mask option register, which is implemented in EPROM, cannot be programmed in user mode, only in expanded test mode. All other EPROM locations can be programmed in user mode by applying the necessary programming voltage on the IRQ/ VPP pin and manipulating the bits in the EPROM Programming Register ($0018) appropriately. 1999Mar04 68HC05, 68HC705B16 Memories How is security enabled in the 68HC705B16 and what does it protect?
The security bit in the 68HC705B16, implemented as bit 0 of the Options register ($100) in EEPROM and referred to as SEC, prevents entry into non-user mode when cleared and thus disallows external access to EPROM and EEPROM1. EEPROM1 is a 256-byte array from $100 to $1FF, while EPROM is the entire programming array from $300 to $3DFF and the user vector area from $3FF2 to $3FFF. When the SEC bit is set, it is in the erased state and access to these memory blocks are enabled in non-user mode. Once activated, this bit can only be deactivated in this OTP device by erasing this EEPROM bit in user mode.
The Options register, since it is within the first 32 bytes of the EEPROM array from $100 to $11F, is not protected from user-mode write/erase. This protection, which only protects the rest of EEPROM from $120 to $1FF, is enabled by the activation of the EEPROM protection bit, which is located at bit 1 of the Options register and is referred to as EE1P. This write protection, however, is only enforced in user mode, not in bootstrap mode.
Since the security bit, as well as the EEP1 bit, is implemented in EEPROM, it is modified by the use of the on-board charge pump and the proper manipulation of bits in the EEPROM control register. Note that the erased state of EEPROM is 1, so that each of these two functions is deactivated when their respective bit is high. 1999Mar04 68HC05, 68HC705B16 Memories What are the failure symptoms of the EEPROM in the 68HC705B16?
Several behaviors are symptomatic of EEPROM failure or failing. They are:
The endurance of the EEPROM in the B16 is specified to be at least 10,000 write/erase cycles, while the data retention is specified to be 10 years @ 85 degrees C. Programming time should be kept to a minimum, as the aggregate amount of time that the programming voltage is applied to a cell directly affects the cells longevity. The specification for both programming and erasing time is 10 milliseconds, but a cell can be programmed sufficiently most of the time in 400 microseconds to 1.2 milliseconds. Using a bump programming algorithm that programs in short increments, like a millisecond, and checks for successful write/erase after each bump before programming again, will result in better endurance for the EEPROM. 1999Mar04 68HC05, 68HC705C8A Memories What is the unprogrammed state for the 68HC705C8A EPROM memory?
The unprogrammed state for the 68HC705C8A EPROM is 0. 1999Mar04 68HC05, 68HC705P6A Memories What happens if the stack space is exceeded in the 68HC705P6A?
The stack space for the 68HC705P6A, as with most 68HC05's, is from $FF to $C0. If the stack overflows, that is, if the amount of data written to the stack fills this 64-byte RAM area and causes the pointer to go past $C0, the pointer wraps around to $FF where data (return address, etc.) are overwritten. This will, of course, prevent return from routines or interrupts whose return addresses were stored there. For this reason, it is a good idea to keep interrupts disabled in interrupt service routines. Note that for 68HC08's, the stack pointer has no such restriction and can be located, either by automatic decrement or by programmatic positioning using the TXS instruction, anywhere in the 16-bit memory area. 1999Mar04 68HC05, 68HC705L16 Memories Where is RAM in the 68HC705L16 and how much of it is used by the stack?
512 bytes of RAM reside in the memory map from $40 to $23F. The stack is located in its standard location starting at $FF and extending down to $C0 (contrary to a statement in the 68HC705L16's data book). The first 192 bytes of RAM, from $40 to $FF, can be accessed by direct addressing, while the remaining 320 bytes above $FF are accessed by extended addressing. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts What is an interrupt?
An interrupt provides a method of temporarily stopping normal program execution to perform a given task. After the task has been completed, normal processing can be resumed.
Interrupts provide a fast, efficient, and automated technique to process tasks and peripherals. They are especially useful for time-critical responses to I/O events or for tasks which require attention at irregular intervals. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts How does an interrupt work?
If an enabled interrupt occurs, the instruction in progress is completed. The processor then saves the current values of the program counter, accumulator, index register, and condition code register onto the stack. The interrupt mask (I bit) is set to prevent additional interrupts.
Each interrupt source (IRQ, Timer, SCI, SPI, SWI) has its own interrupt vector, typically located in the last block of the memory map. These locations can vary between parts. The high and low bytes of a particular interrupt vector tell the processor where to find the interrupt's service routine. When an interrupt occurs, this address is fetched and loaded into the program counter.
To return from the interrupt, the RTI instruction is used. This should be the last instruction in an interrupt's service routine. The RTI instruction restores the values of the condition code register, accumulator, index register, and program counter from the stack. This returns the processor to its state before the interrupt occurred. The I bit is reset if the I bit stored on the stack is 0. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts What types of interrupts are there?
Interrupts fall into three categories: reset, software, and hardware.
A reset condition is similar to an interrupt, because it causes the MCU to fetch a new address for the program counter and sets the I bit to mask interrupts. The processor is configured to a known state as described in the data book for the MCU being used. Resets can be caused by a signal on the external RESET pin or an internal reset signal which can be caused by the COP module or the clock monitor.
A software interrupt occurs as a result of the SWI instruction. A software interrupt causes the same actions as a hardware interrupt; the program context is stacked, the I bit is set, and the interrupt vector is fetched. Another important difference between software and hardware interrupts is that context is stacked, the I bit is set, and the interrupt vector is fetched. The important difference between software and hardware interrupts is that the software interrupt is nonmaskable. In other words, the value of the I bit has no effect on the software interrupt. A software interrupt is always executed.
A hardware interrupt is generated by internal or external hardware conditions. This type of interrupt can be initiated by hardware pins or modules. Hardware interrupts are maskable, so they can be recognized only with the I bit cleared. Each module has its own interrupt vector, but interrupt sources within the same module can share the same vector. For this reason, it is important to arbitrate interrupts which share an interrupt vector.
Common MCU hardware interrupt sources:
IRQ:
The IRQ pin can be used to trigger external hardware interrupts. Depending on the MCU configuration, a logic low or a high-to-low transition on this pin will cause an IRQ interrupt. This interrupt can be used to monitor external systems or events.
Timer:
The 16-bit timer on a Motorola MCU can generate several different interrupts, depending on the particular part used. The output compare, input capture, and timer overflow functions of the timer module can generate interrupts. Some parts also have a real-time interrupt feature. These types of interrupts can be used to process events based on time references.
SCI/SPI:
Parts equipped with SCI or SPI serial ports can generate a variety of interrupts, depending on the part used. These include receive register full, transmit register empty, and transmission complete interrupts. These types of interrupts can be used to process serial communications events.
I/O Port Pins:
Some Motorola MCUs have the ability to use I/O port pins to generate hardware interrupts. These combine with the IRQ pin to form one source of hardware interrupts. Each interrupt source has a specific priority, determined by the device. For information on interrupt priorities, consult the data book for the device. 1999Mar04
68HC05, 68HC08 Exceptions, Interrupts How are interrupts enabled or disabled?
Maskable interrupts are globally enabled by clearing the I bit in the Condition Code Register (CCR). Use the CLI instruction to clear the I bit. Use the SEI instruction to set the I bit, thus inhibiting interrupts from being serviced.
The individual interrupts generated by the MCU modules (SCI, SPI, Timer, etc.) are enabled or disabled by their enable bits in the applicable control registers. To enable these types of interrupts, both the I bit and the enable bits must be appropriately configured. This allows a programmer to implement an application-specific combination of interrupts.
Take the 68HC705P6A MCU as an example. If one wanted to use the input capture function of the timer subsystem to cause an interrupt, the programmer would need to set the Input Capture Interrupt Enable (ICIE) bit of the Timer Control Register (TCR), then use the CLI instruction to start servicing interrupts. The Timer Vector ($1FF8 to $1FF9) should contain the address of the timer's interrupt service routine.
A software interrupt is non-maskable. Therefore, it is always enabled. The I bit has no effect on execution of the SWI instruction.
IMPORTANT:
On reset, the I bit is set. Therefore, it is necessary to clear the I bit before interrupts are expected to be serviced. To properly set up interrupts, the programmer should always configure control registers, set/clear interrupt enable bits, then clear the I bit. 1999Mar04
68HC05, 68HC08 Exceptions, Interrupts How do I use interrupts which share the same vector?
When using interrupts which share the same vector, the interrupt service routine at the address pointed to by the interrupt vector must perform arbitration to determine which source caused the interrupt. This can be done by monitoring the flag bits in the appropriate status register. The flag bits will indicate which source caused the interrupt. Of course, arbitration is unnecessary if only one interrupt source for a shared vector is enabled.
Using the 68HC705P6A MCU as an example, the Timer Vector ($1FF8 to $1FF9) is shared by three interrupt sources: Input Capture, Output Compare, and Timer Overflow. Because an interrupt from these sources will cause a program to jump to the same address, the interrupt service routine must resolve the origin of the interrupt. The Timer Status Register (TSR) contains flag bits for the three timer interrupt sources.
Once the interrupt source is determined and has been serviced, it is very important to clear the interrupt flag in the status register. If this is not done, a duplicate interrupt may occur after returning from the current one. Consult the particular MCU's data book for details on clearing its flag bits. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts How should I handle unused interrupts?
It is good programming practice to address all interrupt vectors, including those that are not used. There are two ways to approach this. One method is to point all unused vectors to an RTI instruction. If a spurious interrupt occurs for some reason, the processor will simply return control and will not get lost.
An example of code to address unused interrupts:
The hazard of using the previous method of addressing unused interrupts is that it may conceal problems which the user wants to be made aware of. To avoid this, consider pointing the unused vectors to a routine which toggles an I/O pin or gives some other indication of a possible problem.
A more fault-tolerant method of handling unused interrupts is to use a "trap" with a COP (Computer Operating Properly) watchdog. This method, with a COP enabled, traps unwanted interrupts in a loop, waiting for a COP reset. This provides a way of resetting the microcontroller when an unexpected condition occurs.
An example of this technique:
NOTE: In certain parts which rely on the values of the user vectors for security, assigning identical address values to unused interrupts may not be acceptable. If this is a consideration, the trap/unused code could be duplicated in different memory locations to further enhance security. 1999Mar04 68HC05 Exceptions, Interrupts Is the RESET pin bidirectional?
The function of the RESET pin can differ from part to part. In some parts this pin is an input only. In other parts, the RESET pin can indicate an internal exception, driven by a COP or clock monitor reset.
For example, the 68HC705C8A has both a programmable and a non-programmable COP. The programmable COP will pull the RESET pin low on an internal reset. However, the non-programmable COP will not pull the RESET pin low when it internally resets the MCU. This behavior provides compatibility with older C4A and C8 MCU designs. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts How do interrupts affect the stack pointer?
The stack pointer can be affected in three ways:
Software will determine how the stack is affected by interrupts. If the user chooses to enable interrupts inside an interrupt routine, then nested interrupts may occur. In this instance, the stack will grow with each interrupt. The stack pointer can address 64 locations. If 64 locations are exceeded, the stack pointer wraps and loses the previously stored information. Care should be taken to avoid this condition.
NOTE: To maintain 68HC05 compatibility, interrupts on the 68HC08 Family do not stack the high byte (H) of the index register. If 68HC08 interrupt code modifies H, it is the user's responsibility to save and restore it. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts Is the timing of interrupt software important?
Yes. The time it takes to process an interrupt is extremely important. An interrupt should be serviced and returned from as quickly as possible. The duration of the interrupt routine will determine how quickly interrupts may happen.
Consider the output compare function of the timer. If the output compare interrupt is used to generate a square wave on the TCMP pin, an interrupt must be generated twice for every period of the desired waveform. If a 10 kHz signal is to be generated, a timer interrupt needs to occur every 50(s. At an internal operating frequency of 2 MHz, a processor clock cycle takes 0.5(s. This would require the interrupt routine to take no longer than 100 clock cycles to execute.
It is important to include the time to vector to the interrupt routine when calculating the speed of the software. It takes nine clock cycles to stack the current program context (the same amount of time as an RTI) before the program counter jumps to the vector address. This should be included in the total clock cycle count of the interrupt routine.
Bottom line: an interrupt cannot be processed faster than the worst-case duration of its software routine. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts What potential problems are there if I disable interrupts to handle time critical tasks?
Under certain conditions, an anomaly occurs when disabling interrupts. This problem was first discovered with the Real Time Interrupt on the 68HC705BD8 (BlueKat). The scenario is:
Starting conditions: Real Time Interrupt is enabled (RTIE = 1) I bit in CCR is cleared.
To disable the interrupt, to do a time critical task, then the code normally would be seen as
Notice that the I bit is left at '0'. Using this code it was discovered that the MCU would sometimes jump to the RESET routine, even though no external reset, watchdog, or s/w "JUMP TO" were seen.
Further investigations showed that if the MCU were to receive an interrupt while executing the disable of that interrupt, then this would happen:
At the last point, the RTIE bit overrides the RTIF bit (or signal) that goes to the "Interrupt Priority" logic. Because of this, the CPU sees that no interrupt is pending, so defaults and fetches the RESET Vector.
In software, this can be overcome by inserting an SEI instruction before disabling the interrupt.
This scenario can be replicated on all 68HC05 devices with the Real Time Interrupt on-board. Further investigation of other interrupts on 68HC05s are being made, and initial findings are that there will be a possibility of this scenario happening with other interrupts.
NOTE: Most customers may never see this scenario, as normally an interrupt is enabled and never disabled thereafter. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts Can a pending IRQ interrupt be cancelled in the IRQ interrupt routine?
An external interrupt event is latched after a small synchronization delay. This latch causes the interrupt process to occur, and after nine cycles the IRQ vector location is read and the latch is cleared.
Another external interrupt pulse could be latched during the IRQ service routine. In this case, with the 68HC05 Family, there is no way to avoid the servicing of the pending interrupt upon returning from the current interrupt (issuing the RTI instruction). When returning from the current interrupt, the I bit will be returned to its value prior to the interrupt.
In the 68HC08 Family, the ISCR (Interrupt Status and Control Register) contains ACK (Acknowledge) bits which can be written to to clear the status of the interrupt latch. In this way, a pending interrupt can be cancelled. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts What signal is applied to the IRQ pin to cause an interrupt?
The sensitivity of the IRQ pin, in most parts, is selectable through an Option Register or Mask Option Register. This pin can be configured for negative-edge or negative-edge and level-sensitive triggering. If configured for level-sensitive triggering, an external pull up resistor should be connected to the IRQ pin.
The specific requirements of the IRQ pin signal are documented in each part's technical data book, in the control timing specification. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts What is an alternative to using interrupts?
One alternative to interrupt-driven routines is polling routines. In a polling situation, status register flags are monitored periodically to determine if service is needed. An example would be monitoring the Serial Port Interface Flag (SPIF) in the SIOP Status Register (SSR) to determine if a data transfer has been completed.
This technique can be easier to implement than vectored interrupts. It can be used when responsiveness is not as critical or when tasks should be serviced at predictable intervals. 1999Mar04 68HC05, 68HC08 Exceptions, Interrupts I understand interrupts, but how do I write the software to use them?
View the example code that demonstrates the implementation of interrupts, including setup, ISRs, interrupt arbitration, and initialization of interrupt vectors. 1999Mar04 68HC05 Exceptions, Interrupts Are interrupts always blocked/disabled in interrupt service routines (is this secure) (automatic set of I bit)? Are interrupts always enabled after RTS (automatic reset of I bit)? Do interrupt requests
Here is the general procedure of interrupts:
Pending interrupts retain their priority levels when the I bit is set, the highest priority routine (if it is pending) will be serviced as soon as the I bit is cleared again (in step 8).
Here is the general procedure of interrupts:
Pending interrupts retain their priority levels when the I bit is set, the highest priority routine (if it is pending) will be serviced as soon as the I bit is cleared again (in step 8).
Sympton:
This problem is usually a marginal rise time or stability issue with the application power supply. It is typical that the problem will be reported as a device power-on repetitive reset problem.
Explanation:
First ensure that watchdog or illegal address reset possibilities have been considered.
To eliminate any device related reset problem, remove or isolate the application power supply from the device and temporarily connect a bench DC power supply with a rise time of a few milliseconds. This should provide a clean power source and eliminate, or at least minimize, possible power supply rise time, spike, or oscillatory issues.
If this procedure proves successful, the customer should be advised to improve the performance of the application power supply. This may involve component adjustment for shorter rise time, ripple reduction, or improved noise immunity. 1999Mar04 68HC05 Exceptions, Interrupts What could cause an unexpected reset after an interrupt event?
Symptom
At irregular times the 68HC05 performs the reset sequence. Instead of fetching an interrupt vector in the range from $FFF0 - $FFFD, the processor fetches the reset vector at $FFFE.
Explanation
This behavior occurs when a peripheral module raises an interrupt, while the currently executed instruction disables or resets this interrupt. The interrupt is recognized by the CPU05 during the opcode fetch cycle.
Since the 68HC05 does not interrupt an instruction, the actual interrupt processing is delayed till the end of this instruction. If, however, this instruction removes the source of the interrupt, the CPU does not know which originating interrupt line the reset vector fetched.
Example 1:
BSET RR,CTL ; set the reset bit in the CAN module
By setting the reset bit, all interrupts pending are cleared. So if a receive interrupt occurs just when the BSET opcode is fetched, this scenario occurs.
Example 2:
BCLR ICIE,TCR1 ; disable input capture by clearing the enable bit
By resetting the interrupt enable bit a interrupt output line is driven to zero. So if a valid input edge occurs at the beginning of this sequence we have the scenario.
Fix:
The fix is to disable the interrupt while modifying the enable bits.
E.g.
SEI
BSET RR,CTL
CLI
This should be done for any sequence affecting interrupt handling. In general disabling interrupts related to external asynchronous events should be performed with caution.
Remark:
In many textbooks this behavior is described as "spurious interrupt", and different MCUs handle it differently.
Examples of similar scenario with other MCUs
An interrupt is occurring for a CAN module, a carry-over from the 68HC705X16 mask. Normally the CAN module in the 68HC705B16 is disabled and a CAN interrupt should not be possible. However, the CAN module circuitry in the 68HC705B16, mask set D28J only (it has been corrected in mask set F56K), may create a pending interrupt immediately after a POWER-ON RESET. That is, when the 68HC705B16 is first powered on, there may be a pending CAN interrupt and the device will service try to service it when interrupts are enabled (by means of a CLI instruction). If the CAN interrupt vector is not initialized to service valid code and a CAN interrupt occurs, the device will very likely run away.
The CAN interrupt's vector location is $3FF0-$3FF1. This is the only interrupt in the device that uses this vector address, and the 68HC705B16 with this mask set may require that a second reset occur after the POR. As the data book suggests, the best way to implement this is to start the watchdog timer after the POR. This is done automatically if the device has the mask option that enables the watchdog upon reset. If this is not the case, the watchdog can be started in software by setting the WDOG bit in the Miscellaneous Register. The watchdog can then be stopped by issuing the STOP instruction, at which time the watchdog reset will occur as if a watchdog time out occurred, which causes the CPU to fetch the address at the RESET vector location ($3FFE-$3FFF). After this second reset has occurred, the device is in a normal operating mode. This process can be done in an interrupt service routine whose vector is stored at $3FF0-$3FF1. The routine itself should have the following:
| CANIRQ | BSET0,$0C | ;Start watchdog (may not be needed if |
| ;mask option enables the watchdog) | ||
| STOP | ;Causes system reset as if a watchdog timeout has occurred | |
| ;vectors to address specified by $3FFE-$3FFF |
When the watchdog resets the circuit, the CAN is then correctly reset and normal execution of the main program can start without being interrupted by the CAN and without re-enabling the watchdog.
It should be noted that in some cases the problem is intermittent and may not appear at each power on. It is also independent of the external RESET circuitry. The problem does not exist on the 68HC05B16 (non-EPROM) device. The time lost between the end of the power-on reset sequence and the watchdog reset is equivalent to 8192 machine cycles (4 ms with 4 MHz crystal). 1999Mar04 68HC05, 68HC705J1A, 68HC05J1A Exceptions, Interrupts Why can't I generate an interrupt when the short oscillator delay bit is enabled?
The SOSCD (Short Oscillator Delay Bit) controls the oscillator stabilization counter and is located in the MOR (mask option register). Coming out of stop mode, the normal stabilization time is 4064 tcyc. By enabling the SOSCD (writing a logic 1) the oscillator stabilization delay is shortened to 16 cycles. This may cause wakeup from STOP functions or POR (power-on reset) to be inconsistent with some oscillator circuits. In newer mask sets, the SOSCD is shortened to 128 cycles as opposed to 16 cycles. This should provide ample time for a good oscillator to stabilize.
old mask set: F44T
new mask set: G58F (RC) / G63P (crystal) 1999Mar04 68HC05, 68HC705J1A Exceptions, Interrupts Does the 68HC705J1A have an internal pull up resistor on reset?
The reset line does not have an internal pull up resistor. It is recommended that a low-voltage inhibit circuit such as the MC33064 be used. The MC33064 will hold the reset line low any time VCC is below the proper operating voltage. An RC can also be placed on the reset line which will pull it high slower than VCC. Using just a pull up resistor is not recommended because the reset line needs a delay at power-on to get a good reset. 1999Mar04 68HC05, 68HC705C8A Exceptions, Interrupts Does the 68HC705C8A have an illegal address reset feature?
No, the 68HC705C8A does not have an illegal address reset. Some promotional literature for the device incorrectly attributed this feature to the 68HC705C8A. The data book is correct. 1999Mar04 68HC05, 68HC705C8A Exceptions, Interrupts Is the RESET pin bidirectional on the 68HC705C8A?
Under certain conditions, the RESET pin will be pulled low by internal circuitry. This indicates some internal error condition. The 68HC705C8A RESET pin will be pulled low by three internal conditions:
The 68HC705C8A RESET pin will not be pulled low by a reset caused by the non-programmable COP. This behavior is consistent with the C4A MCU (which had the non-programmable COP). 1999Mar04 68HC05, 68HC705C9A Exceptions, Interrupts What are the interrupt level options in the 68HC705C9A?
The triggering mode of an external interrupt is selectable in both C9A and C12 mode as either edge-only triggered or edge and level triggered. This trigger option is determined by the setting of the IRQ bit in C9A Option Register when the device is in C9A emulation mode and by the setting of the C12IRQ bit in the C12 Mask Option Register when the device is in C12 emulation mode. The setting is applicable to the Port B interrupts, when enabled, and for the IRQ interrupt. 1999Mar04 68HC05, 68HC705B16, 68HC05B16, 68HC705B32, 68HC05B32, 68HC05B6 Timer How do I use 68HC05 "B" Family COP watchdog timer? The watchdog on the 68HC05B Family devices is controlled by the WDOG bit in the MISC register ($0C).
On all the ROM devices ( 68HC05B6,HC05B8, 68HC05B16, 68HC05B32) there are two mask options that affect the state of the watchdog . These are:
WAIT MODE
With mask option 2 ENABLED and the MCU enters WAIT mode with the watchdog on, the watchdog circuit may not be refreshed before the time-out period lapses. This is because no CPU instructions are executed in WAIT mode and so no refresh of the watchdog counter can occur. Thus after the watchdog times out a reset will be generated, bring the MCU out of wait mode. If mask option 2. is DISABLED then the watchdog counter is reset and disabled. On exiting WAIT mode (via any interrupt) the watchdog will be enabled again and resume normal operation. If WAIT mode is exited via an external reset then the watchdog will resume the state as dictated by mask option 1.
On the EPROM devices (68HC705B5, 68HC705B16, and 68HC705B32) the two mask options are replaced by two bits located in the MASK OPTION* register, RWAT and WWAT. These bits are EPROM cells that when in the erased state the option is
disabled. Programming these bits to a '1' will enable the relevant mask option.
MCU Addr of MOR HC705B5 $1EFE HC705B16 $3DFE HC705B32 $7FDE
In the case of the watchdog being disabled after POR and reset the user can enable it by writing a '1' to WDOG bit. This will clear the watchdog counter and enable counting. To ensure there is no watchdog time-out , thus causing a reset, the WDOG bit must be regularly updated by writing a '1' to the watchdog refresh bit. Writing a '0' to the WDOG bit will have no effect on the watchdog system.
RESET
If the watchdog is allowed to time-out, a reset is generated. The reset is achieved by activating a pull down transistor connected internally to the RESET pin. This causes the MCU and all other functional blocks to be reset, as would be exhibited with an external reset. The external pull up resistance to VDD should be greater than 30 Kohms to ensure that the watchdog reset is executed correctly. If this load is decreased, then the watchdog reset may not occur. The watchdog reset will normally be seen as an active low pulse of three oscillator cycles. Once the watchdog reset occurs, the MCU will monitor the RESET pin until a logic 0 is seen, then switch off the pull down transistor. This means that if a large capacitor is used for a long power-on reset time, the watchdog reset will not actually occur until the capacitor has been discharged to a logic 0. The pull down device has an equivalent resistance to VSS of approximately 200 ohms. The MCU will accept a VOL of a maximum 1.8 V. Discharge Equation:
This means that the MCU will not recognize a reset until approximately 10mS after the watchdog reset. After the watchdog reset has occurred the watchdog system will be in the state dictated by mask option 1. If the watchdog is to be enabled after reset then the watchdog counter also will be reset.
STOP
The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is executed while the watchdog is enabled, then a watchdog reset will occur as if there was a watchdog time-out. In the case of a watchdog reset due to a STOP instruction, the oscillator will not be affected, thus there will be no tPORL cycles start-up delay. After the watchdog reset has occurred the watchdog system will be in the state as dictated by mask option 1. If the watchdog is to be enabled after reset the watchdog counter will be also be reset.
Time-out Period
The watchdog counter is a 3-stage counter which is clocked from the carry output from bit7 of the free running timer. A time-out will occur when the 3-stage counter has the value '7'. Once the watchdog reset has occurred the counter will also be reset to 0. Writing a '1' to the WDOG bit will clear the 3-stage counter to 0.
The watchdog can be enabled at any time with software. Therefore, the time-out period of the first count can vary depending on the carry output of bit 7 of the free running timer. The minimum time out period would be 6 states, and the maximum time out period is 7 states of the watchdog counter.
Minimum time-out period = 6 states of the watchdog Timer = 6 x 1024 CPU cycles = 3072 CPU cycles Maximum time-out period = 7 states of the watchdog Timer = 7 x 1024 CPU cycles = 3584 CPU cycles
Software Control
When implementing the watchdog, care should be taken on the number of places the watchdog is refreshed by the user software. In the case of the 68HC05B6 the minimum time-out is 3072 CPU cycles, which for an average of 4 cycles per instruction would be 768 instructions. A good design would be that the software would refresh the watchdog approximately every 700 instructions. This would allow a minimum number of watchdog refresh instructions in the user software, thus reducing the probability of code run-away refreshing the watchdog.
In the case of the larger ROM devices as with the 68HC05B16 and 68HC05B32, be careful that the ROM memory map does not have a refresh of the watchdog in every 1 Kbyte of code. This would make the chance of a watchdog time-out less if runaway was to occur. A small main loop with one refresh of the watchdog is the ideal scenario, where the main loop is a series to JSR (jump to subroutine) instructions. Watchdog refreshes should be avoided in interrupt routines and subroutines if possible to avoid run-away code refreshing the watchdog. 1999Mar04 68HC05, 68HC08 General I/O How do I use an I/O pin as an interrupt source?
In parts which have this capability, there are typically three considerations to allow an interrupt from an I/O port:
For example, to use a Port B pin as an interrupt on the 68HC705C8A, one must program a one to the Port B pullup bit (PBPUx) in MOR1, and program a 0 in the Port B data direction bit (DDRBx).
The method of enabling external interrupts on ports varies among MCUs. Consult the data book for the MCU you are using. In most cases, the additional interrupt lines are internally ORed with the IRQ line to form one interrupt source. The port interrupt lines are subjected to the same timing and sensitivity (edge/edge and level) considerations as the normal IRQ line.
IMPORTANT:
BIH or BIL instructions test voltages on the physical IRQ pin. The BIH or BIL instruction may not be used to test for port interrupt pin status. These interrupt pins should be tested by reading the data register location for the pin. 1999Mar04
68HC05, 68HC08 General I/O How can I avoid pin damage?
The two important conditions to guard against are operating outside of specified maximum or minimum voltages and currents. One should take every step necessary to ensure that the voltages at an I/O pin stay within the specified ranges.
If the possibility exists of an input exceeding voltage limits (i.e., below VSS or above VDD), a current-limiting device (resistor) should be considered. Internal diodes will latch the input voltage to a diode drop above VDD or below VSS. At that point, there is nothing internally which considered. Internal diodes will latch the input voltage to a diode drop above VDD or below VSS. At that point, nothing internally will limit current flow. The user should ensure that voltages at an input remain within the recommended range.
Zap refers to damage caused by very high-voltage static electricity exposure. Be careful during handling and assembly of MCUs, to avoid exposing the part to such voltages.
Latchup refers to the unintentional activation of parasitic transistors. This can occur with the application of voltages above VDD, or below VSS. Be careful to avoid exposing I/O pins to voltages or currents which exceed those stated in the electrical specification. 1999Mar04 68HC05, 68HC08 General I/O How should I deal with unused pins?
The treatment of unused I/O pins may vary with an application's cost, environmental, and noise requirements.
Because 68HC05 and 68HC08 MCUs are CMOS devices, unused input pins should be terminated to ensure proper operation and reliability. If an input pin is left floating, it can cause oscillation, noise, and excessive current consumption.
The best method to terminate unused inputs is with a pull up or pull down resistor for each unused pin. Sometimes input-only pins are connected to each other, through a common termination point and resistor. Although this is an inexpensive solution, it is much harder to use one of these pins if needed later. Inputs can be connected directly to VDD or VSS, however this makes it more difficult to change the level at that input. If a resistor is used to pull up or pull down the input, then a signal can be connected more easily at a later time.
Unused input/output (bidirectional) pins may be connected to VDD or VSS through a resistor for each individual pin. ins configurable as outputs should not be connected directly to VDD or VSS.
Some applications leave these pins unconnected and reconfigure them as outputs (through software) during initialization. This can be adequate for higher speed applications involving clock sources with fast startup times. There is still a brief period during reset and initialization where these pins are unterminated inputs. There is also the possibility of a malfunctioning MCU failing to properly switch these pins to outputs.
The liberal use of pull up/pull-down resistors can reduce both current consumption and the possibility of electrostatic damage. The use of individual resistors for each pin can make future expansion and reconfiguration easier. 1999Mar04 68HC05, 68HC08 General I/O Besides outputting logic levels, what other capabilities do I/O pins have?
Depending on the part, I/O pins can have many different features. Here are some of the various characteristics of I/O pins:
Data Direction
Some pins are bidirectional, while others are input only or output only.
External Interrupt Capability
Certain parts have I/O pins which can be programmed to generate external interrupts. On some parts, these ports are connected directly to the external interrupt line, ORing themselves with the IRQ input. On other parts, the pins are used as a KWI (keyboard wakeup interrupt) for keyboard input. Some provide a second (IRQ2), independent interrupt source.
High Current Sink/Source
Some MCUs have pins which can sink more current than others. This provides the capability to drive LEDs or other similar loads. Some pins can both source and sink extra current.
Alternative Outputs
The output pins of some MCUs can be driven by alternate sources. For example, the 68HC705B16 MCU can output the internal CPU clock to one of its port pins. The 68HC705JP7 has a pin which can be driven by the output of an internal voltage comparator.
Shared Functions
Many of the MCU port pins are shared with other MCU subsystems such as serial interfaces, A/D converters, or timer functions. 1999Mar04
68HC05, 68HC08 General I/O What is a port data register?
From a programming perspective, an I/O port is made of several components. Each port has a data register, represented by a memory address. In M68HC05 and M68HC08 devices, these are typically the first locations in memory. For example, the 68HC705C8A has four I/O ports: A, B, C, and D with four memory addresses. These are located at $0000, $0001, $0002, and $0003, respectively.
If a port pin is configured as an output, a write to its data register bit is placed in the output buffer and is transferred to the pin. If configured as an input, a read from a data register location will return the current value of the pin. 1999Mar04 68HC05, 68HC08 General I/O What happens if I write to an input port pin or read from an output port pin?
The direction of the port pin, determined by the data direction register, decides whether an action involves the data latch or the actual pin.
In input mode, a read returns the status of the port pin. If a pin is configured as an input, and a write is made to the corresponding bit in the data register, then the data is written to the output buffer (data latch) without affecting the pin value.
If a pin is configured as an output, a read will return the value in the output buffer.
The following table summarizes the result of read/write actions on input/output port pins. The chart assumes a bidirectional port pin.
| R/W' * | DDRn | Action of MCU write to/read of data bit |
| The I/O pin is in input mode. Data is written into the output data latch. | ||
| Data is written into the output data latch, and output to the I/O pin. | ||
| The state of the I/O pin is read. | ||
| The I/O pin is in output mode. The output data latch is read. |
* R/W is an internal signal. 1999Mar04 68HC05, 68HC08 General I/O, Electrical Specification How do I determine the electrical characteristics of an I/O pin?
For the electrical specifications of an I/O pin, consult the part's Technical Data Book or General Release Specification.
Look at the DC Electrical Characteristics table for the corresponding operating voltage ( VDD). The headings "Output High VOLtage" and "Output Low VOLtage" show the maximum current loads which guarantee proper operation.
| Characteristic | Symbol | Typ | Max | Unit | |
| Output High VOLtage (Iload= -2.5 mA) PA4-PA7 (Iload= -5.5 mA) PB2-PB3, PA0-PA3 | |||||
| Output Low VOLtage (Iload= 10.0 mA) PB2-PB3, PA0-PA7 | 0.8 |
This table is taken from the MC68HC705KJ1 Technical Data book. The specification for Iload in the Output High VOLtage category is the guaranteed current source capability at the specified VOH. Likewise, the Iload in the Output Low VOLtage category is the guaranteed current sink capability at the specified VOL. Many of our data books also show the typical port characteristics across different VOH and VOL.
The 68HC705KJ1 MCU has LED drive capability on all port pins. LED drive is provided by allowing a pin to sink a typical LED current (~10 mA). This is reflected in the Output Low VOLtage (sinking current) specification. The table shows that each Port A pin can sink up to 10.0 mA. Under the Output High VOLtage category, we see that PA4-PA7 can source 2.5 mA at a VOH of 0.8 V, while the other port pins can source 5.5 mA at the same VOH.
IMPORTANT:
There is a significant difference between the maximum ratings for current and voltage, and operating current and voltage. The "Maximum Ratings" tables show the limits to which the MCU can be exposed without permanently damaging it. If a part is exposed to the maximum ratings, it is not guaranteed to operate properly. For example, the 68HC705KJ1 specifies a maximum of 25 mA per pin. Operating at that current may affect long-term reliability through metal migration. For long-term reliability, Motorola recommends following the specified Iload vs. VOH and VOL. 1999Mar04
68HC05 General I/O What is a port data direction register?
Each bidirectional (input and output) port has its own data direction register. These addresses typically come immediately after the locations of the data registers. In the 68HC705C8A, the data direction registers are at $0004, $0005, and $0006 for port A, B, and C, respectively. Port D on the 68HC705C8A is an input-only port. Therefore, it does not have a data direction register.
The bits in a port's data direction register reflect the direction (input or output) of its pins. A value of 0 in a data direction register configures a port pin as an input. A value of 1 configures a pin as an output. On reset, bidirectional port pins are configured as inputs, as bits in the data direction register are cleared on reset.
IMPORTANT:
To avoid a glitch on the output pins, write data to the I/O Port Data register before configuring it as an output. This will ensure the desired output level at the pin when it is switched to an output. 1999Mar04
68HC805PV8, 68HC05PV8 General I/O, Analog HC805PV8 - Can I program only one bit of Port A as an analog input, and the other bits digital inputs and digital outputs? I plan PA1 = analog in, PA0, 4, 5 = digital outputs PA2, 3, 6 ,7 = digital inpu
Yes, program PA 1,2,3,6,7 as inputs via DDRA, program PA 0,4,5 as outputs via DDRA and select PA1 as analog input via ADSCR
Yes, program PA 1,2,3,6,7 as inputs via DDRA, program PA 0,4,5 as outputs via DDRA and select PA1 as analog input via ADSCR 1999Mar04 68HC805PV8, 68HC05PV8 General I/O HC805PV8 - I am not able to make Port C function as digital input(s). Individually or as a group, nothing works as an input. All bits on Port C work as digital outputs. Does Port C function as inputs, o
Port C0 to C4 can be configured as inputs. Port C5 and C6 are open-drain outputs only.
Port C0 to C4 can be configured as inputs. Port C5 and C6 are open-drain outputs only. 1999Mar04 68HC805PV8, 68HC05PV8 General I/O Port C bit 4 is the ISO9141 communication bit. I assume this single bit can be programmed as an input and an output (at different times) to perform communication. Am I correct? Yes. 1999Mar04 68HC805PV8, 68HC05PV8 General I/O We got PC4 to work at 9600 baud input. Wrote 08 to MFTEST register. 08 = LSOFF Setting LSOFF = 1 does not disable the PC5 and PC6 outputs as indicated in the manual. Manual is General Release Specificat
To clarify the biasing schemes:
We have currently the following mask sets
G91G is the Puck
G45V is the Puck2
H81A is the Kobold 805
J47D is Kobold2 805
From a software point of view, J47D and H81A are identical. G91G and G45V both differ from H81A and J47D.
The Specification Rev1.2 and Rev 1,3 cover the H81A/J47D silicon.
The Bit 3 in the MFtest register control the following on the J47D:
Most likely, the emulator has got G45V (Puck2, Rev0.9 of the spec is valid.
By setting the Bit3 of the MFtest register, PC5 and PC6 outputs, temperature sensor and PC0. PC4 inputs are de-biased and non-functional. PC4 output is not affected.
If the emulator has got G91G (Puck1) silicon, suggest replace it with H81A or J47D silicon, since the PC0. PC6 output structure is very different as is the biasing scheme.
To clarify the biasing schemes:
We have currently the following mask sets
G91G is the Puck
G45V is the Puck2
H81A is the Kobold 805
J47D is Kobold2 805
From a software point of view, J47D and H81A are identical. G91G and G45V both differ from H81A and J47D.
The Specification Rev1.2 and Rev 1,3 cover the H81A/J47D silicon.
The Bit 3 in the MFtest register control the following on the J47D:
Most likely, the emulator has got G45V (Puck2, Rev0.9 of the spec is valid.
By setting the Bit3 of the MFtest register, PC5 and PC6 outputs, temperature sensor and PC0. PC4 inputs are de-biased and non-functional. PC4 output is not affected.
If the emulator has got G91G (Puck1) silicon, suggest replace it with H81A or J47D silicon, since the PC0. PC6 output structure is very different as is the biasing scheme. 1999Mar04 68HC705B32 Electrical Specification What are the IDD values for the 68HC705B32?
The following are preliminary estimates of the 68HC705B32 power consumption. When the device is fully characterized a rev 5 of the data book will be published with final values.
Supply Current for 5 V Operation (page H23)
| RUN (SM=0) IDD TYP = 3.6 | MAX = 6 mA | |
| RUN (SM=1) | IDD TYP = 0.9 | MAX = 3 mA |
| WAIT (SM=0) | IDD TYP = 1.1 | MAX = 2 mA |
| WAIT (SM=1) | IDD TYP = 0.7 | MAX = 1.8 mA |
| STOP 0-70 | IDD TYP = 10 | MAX = 20 uA |
| -40 to 85 IDD | TYP = 10 | MAX = 20 uA |
Supply Current for 3.3 V Operation (page H24)
| RUN (SM=0) | IDD TYP = 1.3 | MAX = 3 mA |
| RUN (SM=1) | IDD TYP = 1 | MAX = 2.8 mA |
| WAIT (SM=0) | IDD TYP = 0.8 | MAX = 1.5 mA |
| WAIT (SM=1) | IDD TYP = 0.5 | MAX = 1.5 mA |
| STOP 0-70 | IDD TYP = 10 | MAX = 20 uA |
| -40 to 85 | IDD TYP = 10 | MAX = 20 uA |
Quiescent Current Values
68HC705V8 Stop Regulator enabled (includes Stop IDD, LVR disabled) = typical value of 600 uA
68HC05V7
Stop Regulator enabled (includes Stop IDD, LVR disabled) = typical value of 250 uA
Reasons for Differences:
Design changes to the V7 voltage regulator module reduced the STOP current. Resistors were re-layed out to reduce the current. However, this made the module larger and the 68HC705V8 could not accommodate this without a large issue. Also, the MOR register on the 68HC705V8 draws current as well.
By : Ken Obuszewski
Date :July '98
Remarks:
The current consumption on the 68HC705V8 is dominated by three factors:
There were design changes made to the V7 voltage regulator module to reduce the STOP current. Resistors were re-layed out to reduce the current. However, this made the module larger and the 68HC705V8 could not accommodate this without increasing die size, and since the V7 was meant to be the production device, it was not a large issue. Also, the MOR register on the 68HC705V8 draws current as well. 1999Mar04 68HC05, 68HC705L1, 68HC05L1 Electrical Specification Why am I seeing high run IDD on 68HC(7)05L1?
If not using the full 4 * 16 segment driving capability of the L1 device it is possible to incur a high run IDD current due to the segment display pins being left unconnected. In order to avoid this it is necessary to connect the unused LCD pins to ground. 1999Mar04 68HC705J1A, 68HC705KJ1 Electrical Specification What is the programming voltage ( VPP) of the 68HC705J1A and the 68HC705KJ1?
The programming voltage for both parts is 16.5 volts. 1999Mar04 68HC705KJ1, 68HLC705KJ1 Electrical Specification What is the difference in power requirements between the 68HC705KJ1 and the 68HLC705KJ1?
The standard version, the 68HC705KJ1, is specified to operate at an internal operating frequency of DC to 4.0 MHz @ 5 V and DC to 2.1 MHz @ 3.3 V.
The 68HLC705KJ1 has the same range of operation but it has been optimized to operate more efficiently at low frequencies, in particular at 16 kHz internal operating frequency. Because of the more efficient oscillator circuit at low frequencies, this version provides a power saving over the standard HC version when operating at low frequencies. This saving is more dramatic the slower the device is operated and the lower the supply voltage is.
For example, a recent test found that at 100 kHz internal operating frequency, the HLC version drew about 17% less current at 3.3 V than the HC version operating under the same conditions. Regardless of the version used, care should be taken in selecting external crystal components to minimize power demand while still guaranteeing proper operation under all expected operating conditions.
Note: The 68HLC705KJ1 is not a low-voltage part. It operates at the same voltages as the standard 68HC705KJ1. The reduction in power consumption is achieved through lower operating frequency. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 Development Tools Who do I call for Motorola development tool warranty service/repairs?
Global Data Specialists handles warranty repairs for Motorola microcontroller development tools in North America. They can be reached at (800) 451-3464 or (602) 437-4331.
For all other regions, please contact your local Motorola sales office or authorized distributor. 1999Mar04 68HC05, 68HC08 Development Tools How do I upgrade from 68HC05 to 68HC08 development tools?
For the MMDS:
For the MMEVS:
For the EVS:
MMEVS and MMDS systems use a modular emulation module (EM) to configure emulation for a particular member of the 68HC05 Family. This modular approach allows each system to be upgraded to support new MCUs at minimal cost. The older non-modular EVMs could not be upgraded. The new modular approach allows each system to be upgraded to support new MCUs at minimal cost. The older non-modular EVMs could not be upgraded. However, the older EVS system allowed some level of upgrading but could not handle low pin count MCUs, large memory MCUs, external bus MCUs, high speed MCUs, or low-voltage MCUs. Current users of EVM and EVS products can continue to utilize these tools for cost-effective emulation/evaluation but may want to upgrade to take advantage of the MMEVS's new capabilities. Motorola recommends that any new purchases should use the MMEVS instead of the EVS. 1999Mar04 68HC05 Development Tools Can an existing 68HC05 EM be used with the MMEVS?
Any EM compatible with the MMDS can be used in the MMEVS. This includes all EMs that have M68EM05xx part numbers (check the user's manual). A few M68HC05xxEM boards may not work in the MMEVS or MMDS. Attempting to use these older designs in the MMDS or MMEVS will result in an error message concerning an improper identification address. Trying to use an older system will not damage either the system or the EM board.
Find out if your existing EM can be used with the new MMEVS by checking the on-line compatibility table. 1999Mar04 68HC05 Development Tools What else is needed to use an old 68HC05 EM with the MMEVS?
The MMEVS and the MMDS utilize configuration files to describe the memory map of the emulating MCU and to provide CHIPINFO. The appropriate configuration/memory file will be needed to use the MMDS or MMEVS. All configuration files are available to download from our EM Config page. 1999Mar04 68HC05, 68HC05X16 Development Tools What potential problems are there when emulating the 68HC05X16 with an M68EML05X32 board?
Symptom:
A customer has experienced problems when trying to emulate an 68HC05X16 using the M68EML05X32 Emulation Board. The problem has manifested itself in two ways:
Explanation:
The symptoms experienced seem to suggest that there is some problem with the memory mapping involved in emulating an 68HC05X16 using the resident device on the M68EML05X32 emulation board (which is an 68HC705X32).
Solution:
The problem was solved by replacing the resident 68HC705X32 device with an 68HC05X16 device.
Root cause fix:
A root cause fix has not yet been found as the severity of the problem is yet to be fully quantified. Only one customer has reported the problem so far. 1999Mar04
68HC05, 68HC705J1A, 68HC705P6A Development Tools The M68HC705JICS, M68HC705P9PGMR, and M68HC705J2PGMR boards have no SOIC programming socket. How do I program SOIC parts?
The boards were layed out to accept an SOIC socket but were not populated to keep the cost of the boards as low as possible. The socket can be ordered from Yamaichi at 408-452-0797 or Emulation Technology at 408-982-0660. The Yamaichi part number for the 16- to 28-lead SOIC socket is IC51-0282-334-1. The Emulation Technology part number is S-SOR-00-028-D. 1999Mar04 68HC05, 68HC705KJ1 Development Tools How do I upgrade a MMEVS or MMDS system to support the new 68HC705KJ1?
The following is needed to emulate the 68HC705KJ1:
To program the 68HC705KJ1, we recommend the M68ICS05KJ In-circuit simulator/serial programmer. If you do not already have a MMDS or MMEVS, we recommend the KITMMEVS05KJ or the KITMMDS05KJ. Each of these kits includes everything you need in one easy to order kit. 1999Mar04 68HC05, 68HC705KJ1 Development Tools How do I upgrade my M68HC705JICS to support the new 16-pin 68HC705KJ1?
Order the M68ADPKJ1 upgrade kit. This kit will add 16-pin DIP and 16-pin SOIC programming capability and 16-pin in-circuit simulation capability to a M68HC705JICS development kit. The upgrade kit also contains a windowed sample of the 68HC705KJ1 and new Windows-based development software. This software is also available to download from our software upgrade page. 1999Mar04 68HC05, 68HC705K1 Development Tools How does the KICS board program 68HC705K1 PEP and EPROM?
When programming the 68HC705K1 on the KICS board, the user types PROGRAM in the DEBUG window. After a couple of instructions of manipulating the hardware, the Programmer Menu pops up. Some users may think that if they select the 'P' option, all of the EPROM memory locations will be programmed. This is incorrect. Only the bulk user EPROM array is programmed. The Personality EPROM and the MOR byte are NOT programmed. You have to program these bytes separately using the 'E' and the 'M' options. 1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) Can the M68HC05 Family be used in a network which runs extended CAN frame format?
The MCAN module has been designed according to CAN protocol 1.2 (standard CAN, 11-bit identifier) as defined by Robert BOSCH GmbH. The two reserved bits, r1 and r0, within the control field are sent as dominant bits and are not evaluated during reception.
Bit r1 of those reserved bits has been redefined within CAN standard 2.0 B (extended CAN, 29-bit identifier). It has been renamed to IDE bit (identifier extension) and distinguishes between extended CAN and standard CAN format.
Because the IDE bit is not evaluated in the MCAN module, an extended, 29-bit identifier frame would be treated as a standard frame, which would lead into a form error.
1999Mar04
68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) When should and how should the single-line CAN mode be used?
The usual CAN configuration uses two signal lines which transmit a differential signal. A differential signal allows redundancy so that the system is less sensitive to bus failures in a disturbed environment. The transmitter and receiver of the MCAN module also can be set in a single-line mode, where only one line is used to transmit the signal. This mode could be used due to these reasons:
One-line communication mode on the receiver side is entered by connecting one input of the internal receive comparator to a fixed reference voltage. The internal 2.5-V ( VDDH) reference should be used to save additional external connections. The switch to VDDH is done in the CCOM register. Three bits have to be taken care of to use 1-line mode: RX0, RX1, and COMPSEL.
On the transmitter side, only one transmit line should be enabled in single-line mode. The unused transmit line should be set into a floating state. This is set up by the appropriate value in the output control register.
The following pictures show the physical schematics of the MCAN physical interface in one-line mode (RX0/TX0 active) and the required register settings which have to be chosen in one-line mode:
One-line mode on TX0/RX0 line:
One-line mode on TX1/RX1 line:
The TX line polarity depends on the external physical interface. The register setup shown here uses positive polarity, as an example of the use of an external bus transceiver.
The COMPSEL bit has to be cleared in one-line mode, which means that both main comparator inputs are compared to each other to recognize a wakeup condition on the bus. Since one comparator input remains connected to VDDH by setting RX0/1, this configuration leads to the comparison of one single bus line with VDDH (bottom sleep comparator SC in the schematics). If COMPSEL would be set in single-line mode, the two middle comparators would be used for wakeup recognition. In this case, one comparator would compare VDDH against VDDH, which is an unpredictable condition. When entering sleep mode this setup could immediately wake up the MCAN module.
NOTE: The CAN command register (CCOM) must not be modified by using the read-modify-write instructions BSET/BCLR. This register is write only and returns the value $FF when reading it. Thus, a BSET instruction would first read $FF, then set a bit and write $FF back to the CCOM register, which would result in a non-functional CAN module. 1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) After the MCAN module is put into sleep mode, why doesn't the oscillator stop?
The oscillator stops only if the CPU executed a stop instruction and the CAN module was set into sleep mode. It remains in stop until either an external interrupt or a CAN interrupt occurs. 1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) Does the M68HC05 Family MCAN (Motorola controller area network) module use the BasicCAN or the FullCAN principle?
The MCAN module's message buffers are implemented as a BasicCAN structure. Three buffers are implemented in RAM - one transmit buffer and two receive buffers - and each is accessible by either the CPU or the CAN bus at the same time. Because the module has two receive buffers, its software can read a received message while another message is being received from the CAN bus. (Refer to How does the Ping-Pong principle of the two receive buffers work?) A BasicCAN structure offers the advantage of having no fixed link between a receive buffer and a message identifier. Instead, a programmable 11-bit identifier filter defines which messages are allowed to be received.
1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) What does an MCAN interrupt handler look like?
1999Mar04
68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) How should a CAN overrun condition be handled?
An overrun condition occurs if both receive buffers are full and a third message occurs. The following pictures illustrate such an overrun event. In this example, receive and overrun interrupts are enabled. Reading of the message buffers is controlled by the MCAN interrupt routine.
1. In this overrun example, the first received message is ready to be read by the CPU, while a second one is received from the bus and written into receive buffer 0. Due to other peripheral interrupts, such as a timer interrupt, the receive interrupt routine cannot start immediately to readout receive buffer 1.
Receive status (RS): 1
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 1
Release receive buffer (RRB): 0
2. The receive interrupt routine starts and reads the message in receive buffer 1. Receive buffer 0 is now full, and a receive interrupt request for receive buffer 0 will be asserted. A third message arrives, which cannot be written into a buffer since the first message buffer is accessed by the CPU and the second one is full. The new message is dropped. This is indicated by the data overrun status bit (DO), which is set. If data overrun interrupt has been enabled in the MCAN control register, the MCAN interrupt line remains asserted, since it is still asserted by the receive interrupt.
Receive status (RS): 13. As soon as the CPU leaves the interrupt routine after reading receive buffer 1 and after releasing this buffer, the CPU will re-enter the MCAN interrupt routine immediately due to the latched receive and overrun interrupt requests. As receive buffer 1 is released, it can be accessed by a new message (B), which may arrive on the CAN bus. The RBS bit was cleared by releasing buffer 1, but it immediately was set again because the control of the buffer 0 is given to the CPU. The RRB bit gets cleared as soon as the controller starts to receive a new message (RS = 1).
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 1
Release receive buffer (RRB): 0
Data overrun (DO): 1
Receive status (RS): 1
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 0
Release receive buffer (RRB): 0
Data overrun (DO): 1
Within the active MCAN interrupt routine, all MCAN interrupt flags have to be checked to start the corresponding interrupt subroutines. In this case, both the receive and the data overrun interrupt subroutines will be executed.
Within the data overrun subroutine the only action is to clear the data overrun status bit by setting the clear overun status bit COS in the CCOM register. 1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) How are the MCAN module registers initialized?
The MCAN registers usually are initialized within a separate CAN initialization routine. For some registers, it is mandatory to be in the CAN reset state during initialization, which is entered by setting the reset request bit in the CAN control register.
These registers are:Acceptance code register (CACC)
Acceptance mask register (CACM)
Bit timing register 0/1 (CBT0, CBT1)
Output control register (COCTRL)
NOTE:
The CAN command register (CCOM) must not be modified by using the read-modify-write instructions BSET/BCLR. This register is write only and returns the value $FF when reading it. Thus, a BSET instruction would first read $FF, then set a bit and write $FF back to the CCOM register, which would result in a non-functional CAN module.
When setting the MCAN out of reset mode (clearing RR bit), remember that the MCAN module doesn't start normal operation immediately. In a normal situation, MCAN waits for 11 consecutive recessive bits on the CAN bus before starting normal operation. If the bus off state is active, MCAN waits for 128 occurrences of 11 recessive bits before starting normal operation.
Therefore, a wait loop after the reset sequence should be added to make sure that no MCAN action, such as a sleep mode request, is activated before MCAN re-enters normal operation mode.
This diagram shows the usual sequence of a CAN initialization routine.
The init routine usually should be executed only after power-on reset. Therefore, the bus off state does not need to be checked, and there is no need to wait for 128 times 11 consecutive recessive bits within the init routine. Usually, bus off failure is handled separately. (For more details, see How should a bus error or bus off condition be handled?)
Here is an example of an MCAN initialization routine written in assembler language. 1999Mar04
68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) How is the 68HC05X microcontroller connected to an external CAN driver?
Most applications today implement an integrated physical bus interface device which is specified for a higher drive current and which includes short-circuit protection and slope control. Some newer interface circuits even integrate an automatic single-wire mode switch, which recognizes an interrupted or short-circuited bus line to GND/ VDD and automatically switches to one functional bus line.
The appropriate physical interface for a system depends on the speed, which is needed for the CAN bus. There are low-speed physical interfaces (<125 kBaud) and high-speed physical interfaces (up to 1 Mbaud).
When using external transceiver devices, the internal comparator logic of the M68HC05 Family is not needed. Only one transmit and one receive line are connected between the microcontroller and the transceiver. The voltage reference pin, VDDH, of the X-microcontroller can be left open, if internally the VDDH reference is connected to one comparator input. This can be done by initializing the CCOM and COCNTRL register for single-line mode. (For more details, see When should and how should the single-line mode be used?)
Two examples of the 68HC05X controller combined with an external transceiver are shown here. When using a Philips PCA82C250, only three pins need to be connected. Use one TX and one RX CAN line (either 0 or 1 can be chosen) in addition to one input/output pin, which controls the output slope of the bus signal and the standby mode of the transceiver. If the port pin is set to low, the output slope will be controlled via the current through the resistor. This is used in applications with lower CAN bus speed. By switching the port pin to high, the transceiver enters the low-power mode because no current passes through the pin.
The second example shows the use of the newer, more sophisticated, low-speed transceiver PCA82C252 or SN65LBC032. This device is connected to VBAT to detect a short circuit to the battery and ground. In case of bus failures, the device automatically switches to single-line mode, which reduces the 68HC05X microcontroller's error handling software.
In addition to the CAN lines TX and RX, three input/output pins and one interrupt/wired or interrupt pin have to be spent to control the transceiver. The connections to EN and NSTB control the mode of operation of the transceiver (sleep, standby), and the input/output line to NWKUP can enable a wakeup request to the powered down transceiver. Feedback of any failure on the bus or of a wakeup is sent to the microcontroller via the NERR line, which triggers an interrupt.
1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) Which bit time should be chosen for a CAN network?
To define bit time and the length of its time segments, some rules have to be followed. The CAN specification defines a bit time consisting of four segments. These segments are:
1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) How does the Ping-Pong principle of the two CAN receive buffers work?
As described, the MCAN module offers two receive buffers which can be accessed by the CPU or the CAN bus. Both buffers alternate with each other to receive data from the bus. This gives the CPU time to read a message buffer while a new message is being received at the same time. The illustrations demonstrate the steps involved during a message reception.
1. Both receive buffers were empty and released to allow reuse by the CAN interface. A new message arrives and will be written into receive buffer 1.
The following phenomenon has to be considered when resynchronization on both edges is selected. In that mode, a transmitter will resysnchronize on positive phase shifts if a dominant bit is sent. If the transceiver delay of that node is larger than the SYNC time quanta, the transmitting node receives its sent bit edge after the SYNC time quanta and then resynchronizes itself. This will result in a variable bit time/baud rate on the bus. In a CAN network with a different bit timing definition in some CAN nodes (for instance, due to different used crystals), this could cause bus failures.
As described earlier, an enhanced CAN protocol was added, which allows phase shifts of a whole bit time after long sequences of equal bits. With these modifications to the original CAN protocol, the resynchronization on recessive-to-dominant edges as well as dominant-to-recessive edges has absolutely no advantage over resynchronization on recessive-to-dominant edges only. The oscillator tolerance is the same for both ways of resynchronization.
Therefore, resynchronization is recommended only on recessive-to-dominant edges. 1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) How is a CAN message aborted?
In some cases, an urgent message gets activated, for example, by the network management software, but the transmit buffer is full. Then the loaded message has to be aborted to release the transmit buffer for the new message.
First the abort transmission bit (AT) in the CAN command register (CCOM) has to be set to request the abortion of a pending transmission. If the transmission is not already in progress, the buffer is released immediately, which sets the transmit buffer access bit. In the case of an enabled transmit interrupt, the transmit interrupt request gets asserted, which allows an orthogonal interrupt handler. Within the transmit interrupt routine the new message then will be copied automatically into the transmit buffer and requested for transmission.
If the transmission already is in progress when an abort request is being received, the abort request remains active and will be evaluated in the next interframe space. In case of lost arbitration on the bus, the abortion of the old message could then be executed as described above. In that case, the transmit buffer would not get released immediately after the abort request, which has to be considered in polling mode when no transmit interrupt is used. The transmit buffer access bit (TBA) in the CAN status register should be polled to indicate the released state before writing the new message into the buffer. Otherwise, the new data get lost without being signaled. 1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) How should a CAN bus error or bus off condition be handled?
Error management can be defined for the lowest level of the OSI reference model, but also for the higher communication levels of this reference model. Only the low-level error management is discussed here.
The definition of the error management depends very much on the intelligence of the physical interface. When using a transceiver with integrated automatic single-line switch, the software for bus error handling gets reduced. In case of an active error, there's no need for a two-line/one-line mode switch by the software, as this is done in hardware by the transceiver itself. Within the error interrupt routine, the status line of the transceiver, which reports failure mode, could be evaluated and reported to the CAN management software.
When using a simple bus transceiver, no function in the physical interface device recognizes a short circuit or interruption of a bus line. Usually the error management software with this type of transceiver just tells the management software that a bus failure has occurred. Extra, costly hardware would be needed for bus failure sensing.
Another possible implementation is a discrete physical interface, where the two-line mode of the MCAN is used. With this configuration, an active error status could trigger a software algorithm within the MCAN interrupt routine to detect a faulty bus line.
Error status:
The error status bit is set when the receive or transmit error counter reaches value 96. The MCAN interrupt handler should give an indication to the CAN management software that the bus may be heavily disturbed. To avoid a resultant bus off state (only produced by transmission), this may lead the management software to stop any further transmission, if possible.
When using the two-line mode with a discrete physical layer, the error status interrupt software could trigger an algorithm to detect possible bus line interruption or short circuits.
Bus off status:
When the bus status flag in the status register CSTAT gets set, a bus off condition is signaled, which means the internal transmit error counter reached the value 255. This state can never be reached, if the node is in receive mode or if there is only one node on the bus. Within the MCAN interrupt routine, the RR bit should be cleared and the management software should be made aware of a problem on the bus.
NOTE:
The error status and bus off bits are level sensitive. But the error interrupt flag is not level sensitive. The interrupt flag gets set only when either bus off or error status bits change. If the error interrupt becomes active due to a set error status bit, the error interrupt flag gets set and will call the MCAN interrupt handler, when the error interrupt has been enabled. After clearing the error interrupt flag within the MCAN interrupt routine, it gets set again only if the bus off state gets active in addition to error status or if error status was cleared and then set again. 1999Mar04
68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Controller Area Network (CAN) What are the considerations when putting the MCAN module into sleep mode?
After requesting the MCAN sleep mode, the CPU usually checks if the sleep state really was entered. The MC68HC05X16 and the MC68HC(7)05X32 microcontrollers offer a sleep flag, which acknowledges the sleep request. This MCAN asleep flag (CAF) is located at bit 6 of the EEPROM/ECLK control register. The MC68HC(7)05X4 microcontroller also offers such a sleep mirror bit, which is located at bit 3 of the port configuration register (SLEEP).
After a successful sleep request, which is indicated by a set sleep flag, a STOP instruction may be entered to power down the CPU. If the sleep flag is not set, a new message may be arrived, which can activate a receive interrupt in case of a valid, accepted message. After a certain waiting time, the CPU could try again to enter sleep mode.
The oscillator clock will stop only if the STOP instruction is executed after the sleep request. Otherwise, only the clock path of the MCAN module is stopped.
There are several reasons why the MCAN module could not enter sleep mode after setting the sleep request bit:
Two application notes deal with this topic:
AN1298/D, Variations in the 68HC(7)05C Family, This application note compares and contrasts the features of all C Family microcontrollers, including:
AN1226/D, Use of the 68HC705C8A in place of a 68HC705C8,
The technical data books for the different parts should also be consulted. 1999Mar04 68HC05, 68HC705C8A, 68HC05C8A, 68HC05C8, 68HC705C9A, 68HC05C9A, 68HC05C4, 68HC705C8, 68HC705C9, 68HC051999Mar04 Misc. What 68HC05 C-Family parts is the 68HC705C8A compatible with?
There are two compatibility considerations: pin compatibility and code compatibility.
Pin compatibility: Except for the 68HC05C0, the DIP, SDIP, and QFP packages of C-Family parts are pin-for-pin compatible. The PLCC package has minor differences among family members. Consult application note AN1298, page 10 for more details.
Code compatibility: There are some differences in code considerations among the different family members. The differences exist between different C-Family members, OTP and ROM parts, and A and non-A parts. These differences include the COP (computer operating properly) features, MOR (mask option register) programming, and the behavior of the STOP instruction. For more information, consult application note AN1298/D. 1999Mar04 68HC05, 68HC705B32, 68HC05B32, 68HC705B16, 68HC05B16, 68HC05B6 Memories How do I use VPP1 with the 68HC05 "B" Family?
The VPP1 pin of the B6 is a very high impedance pin that is normally not used by the customers application. This pin is used by the tester in the factory. The high impedance can cause problems with some applications. Very high humidity or very noisy environments may cause programming problems so the following is a quick look at what to do with VPP1.
If the application does not write to or erase the EEPROM1 array during normal use, connect the VPP1 pin to VDD.This will ensure that no noise will influence the EEPROM circuit.
If the application does write to or erase the EEPROM1 array during normal use, shield this pin as much as possible. Use plenty of GND track nearby. Some customers have placed a small capacitor (1 nF) to decouple the VPP1 pin. This should not affect the programming in normal use (10 mS programming time) despite slightly lengthening the rise time of VPP1. 1999Mar04 68HC05, 68HC705C8A, 68HC05C8A, 68HC05C8, 68HC705C9A, 68HC05C9A, 68HC05C4, 68HC705C8, 68HC705C9, 68HC051999Mar04 Misc. What are the major differences amoung the 68HC05 "C" Family MCUs?
View the C Family Matrix. 1999Mar04 68HC08 Misc. Why can't I change the values in the CONFIG1 or CONFIG2 registers more than once?
The CONFIG1 and CONFIG2 registers are write-once registers, and can be changed only once after each reset. Do not use consecutive BSET or BCLR instructions on these registers, as only the first such instruction will cause a change. The values should be written once to each of these registers with an immediate addressing MOV instruction. 1999Mar04 68HC08 Clocking Do I always need a filter capacitor on the CGMXFC pin?
If the PLL is used, a filter capacitor should always be used with CGMXFC. If the PLL is not used, this pin can be connected to VSS. 1999Mar04 68HC05, 68HC705C8A, 68HC705C8 Misc. What improvements on the 68HC705C8 are made in the 68HC705C8A?
For more information, consult application note AN1226/D, Use the 68HC705C8A in Place of a 68HC705C8. 1999Mar04 68HC05, 68HC705X32, 68HC05X32, 68HC705X16, 68HC05X16, 68HC705X4, 68HC05X4 Development Tools Why does my 68HC05 "X" Family emulator stop working if I program the SEC bit?
Do not set the SEC bit ($0100 bit 0) while emulating. Setting this bit prevents access to test mode. As the EM board uses test mode, this will cause the device to stop functioning.
Once the SEC bit has been set, it may be cleared by entering the serial bootloader mode with a PGMR board or by UV erasing the part if it has a window. UV erasing will erase both EPROM and EEPROM, thus clearing the SEC bit to the erase state. 1999Mar04 68HC05, 68HC705L5, 68HC05L5, 68HC705L16, 68HC05L16 Misc. What are the differences amoung the 68HC05L5, 68HC705L5, 68HC05L16, and 68HC705L16?
The differences are listed in this table:
1999Mar04
68HC05, 68HC705C9A Misc. What are the two modes of operation in the 68HC705C9A?
The 68HC705C9A can be set up to emulate either an 68HC05C9A or an 68HC05C12A. This table highlights the capabilities and features of each mode of operation.
| RAM | 176-352 bytes | 176 bytes | 176 bytes in C9A emulation can be mapped as RAM or EPROM |
| EPROM | 16 Kbytes | 12 Kbytes | |
| Mask Options | Controlled by C9A Mask Option Register (IRQ sensitivity,RAM0 and RAM1 memory configuration) | Controlled by C12 Mask Option Register (IRQ sensitivity, STOP disable, COP enable, security enable) | C9A/C12A Mode select in C12 mask option register selects which mask options can be set and followed |
| COP Control | Controlled by C9A COP Control Register (COP Flag, clock monitor enable, COP enable, COP time out mode bits) and C9A COP Reset Register | Controlled by C12 Mask Option Register and C12 COP Clear Register | |
| COP Reset | Caused by alternately sending $55 and $AA to the C9A COP Reset Register | Caused by writing a zero to bit 0 of the C12 COP Clear Register | |
| Port D | I/O - Port D DDR controls data direction | Input only - no DDR | |
| SPI | DDR of port D must match output signals for the SPI when using the SPI | SPI not under DDR control | |
| Port D Open Drain Output Capability | Selectable | Not supported | |
| RESET Pin | Bidirectional | Input only | The RESET pin in C9A mode can be driven low by a COP or clock monitor time out or during POR |
The A strategy was introduced to enhance the features that the device offers, including:
The 68HC705P6A is a pin compatible upgrade of the 68HC705P6 with these differences:
Carefully review all options selectable by the new MOR before using 68HC705P6 code in a 68HC705P6A. To configure a 68HC705P6A to operate like a 68HC705P6 without any enhancements, make sure the MOR at $1EFF is programmed to all 0s (disable pull ups/interrupts on port A) and that bit 7 of the MOR at $1F00 is programmed to 0 (disable secure mode).
Motorola's M68HC705P9PGMR programs 68HC705P6As without modification, using the same VPP and following the same procedure as programming 68HC705P6s. If you are using a third party programmer, make sure you contact the manufacturer for a possible software upgrade to support programming 68HC705P6As. 1999Mar04 68HC05, 68HC705P6A, 68HC705P6 Misc. How do I convert from the 68HC705P9 to the 68HC705P6A?
The 68HC705P6A is a pin compatible upgrade of the 68HC705P9 with the following enhancements:
The 68HC705P9 mask option register (MOR) is located at $0900 and is used to control the following options:
The 68HC705P6A uses address $0900 for EPROM/OTP program area. Two new mask option registers are used on the 68HC705P6A:
Carefully review all options selectable by the new MORs and the memory map before using 68HC705P9 code in a 68HC705P6A.
Motorola's M68HC705P9PGMR programs 68HC705P6As without modification, using the same VPP and following the same procedure as programming 68HC705P9s. If you are using a third party programmer make sure you contact the manufacturer for a possible software upgrade to support programming 68HC705P6As. 1999Mar04 68HC05, 68HC705J1A, 68HRC705J1A, 68HSR705J1A, 68HSC705J1A Misc. What special versions of the 68HC705J1A are available?
The 16-pin 68HC705KJ1 is software compatible with the 20-pin 68HC705J1A.
Pay attention to the seven key differences. 1999Mar04 68HC05, 68HC705C9A, 68HC705C9 Misc. What are the differences between the 68HC(7)05C9 and 68HC(7)05C9A?
The 68HC(7)05C9A is an enhanced version of the 68HC(7)05C9. In addition to being shrunk to a more advanced process technology, this device offers the following attributes not available on the 68HC(7)05C9:
Programs written for the 68HC705C8 can be transferred to the 68HC705C8A, provided two locations $FF0 and $1FF1 are programmed with $00.
It is highly recommended that users refer to Motorola application note AN1226/D before using the 68HC705C8A.
Programming the 68HC705C8A
The 68HC705C8A can be programmed with the MC68HC05PGMR-2 and compatibility with the 68HC705C8 can be maintained if the EPROM 2764/27128/27256 location $1FF0 and $1FF1 are programmed with $00. Note that the default value of the unprogrammed locations may be different on different types of EPROMs.
The following discussion will refer to the programmer board MC68HC05PGMR-2.
Programmer Settings
The parallel mode settings are as follows:
Programming Module Preparation
The PGMR must be prepared/configured prior to any program/verify operations. Board preparation consists of external power source (+5 V and VPP), EPROM installation, DIP PGMR configuration and PLCC PGMR configuration.
External Power Source
Power connector P1 is used to connect an external power supply to the PGMR. A +5 V @ 100 mA power source is connected to connector P1 pins labeled +5V and GND. The programming voltage power source is connected to pins labeled VPP and GND. Refer to the 68HC705C8A data sheet for programming voltage ( VPP) specifications.
NOTE: The programming voltage ( VPP = 14.5 V to 15 V) must be measured at SKT2 pin 3 during the programming cycle (D6 PROGRAM LED illuminated).
EPROM Installation
The basic EPROM device used on the PGMR (at location U2) is a 2764, 8 K EPROM, 28-pin device. This EPROM device contained the user code to be programmed into the 68HC705C8A.
Programming Operation
To program the 68HC705C8A MCU, perform the following steps:
Latchup is the breakdown of parasitic bipolar transitors within the MOS device. It results in shorting VDD to VSS, which can cause chip self-destruction or at least the requirement to power down and then power back up. Latchup is most likely to occur in I/O devices, where large currents flow, when the voltage on the pin is taken out of spec.
In an n channel CMOS device, one of the bipolar transistors (a pnp) sets up with its base in the n-substrate, connecting the p-type source of VDD to the p-well. The other bipolar transitor (a npn) is aligned with its base in the p-well and connects the n-substrate to the n-source of VSS. There is a substrate resistance, Rs, and a p-well resistance, Rw.
In the case of the npn transistor, current will flow from the collector to the emitter if the collector is biased positive with respect to the emitter and the base is about 0.6 V more positive than the emitter.
The pnp transistor conducts from emitter to collector if the emitter is biased more positively than the collector and the base is about 0.6 V more positive than the emitter.
If the current injected into the n-substrate and collected by the p-well is high enough, the voltage drop across Rs can rise to the point where the two bipolar transistors turn on and operate in a low resistance mode. Under this circumstance, the VDD to VSS path can become shorted out and cause circuit failure.
Most of what can be done to prevent latchup is done during the design and lay out of the microcontroller itself. Operating the microcontroller within its specification is the best way a board level designer can avoid latchup.
Symptoms:
Latchup is self-perpetuating once it is started, so its symptoms may be there after the cause of it is gone. The way to stop the latchup process is to remove the power from the chip.
Debugging:
Latchup is almost always the result of pulling a pin above VDD or below VSS, so check all pins for this.
Also, be warned that this could be the result of glitches on the pins, so finding the source could require a very tedious debugging session. One way to find an offending pin is to disconnect all inputs and step through trying them either high or low one at a time and then cycle the power and test for when the latchup condition occurs. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 Development Tools How can I interface the MMDS or MMEVS emulators to a QFP surface mount target board?
Motorola provides TQPACK adapters (specific to each package type) to be surface mounted to your target system, using approximately the same footprint as the chip package. The TQPACK has a number of pins on the top which interface to a TQSOCKET with guides. The TQSOCKET protects the fragile pins (it is not easy removing a soldered TQPACK!) and can be easily replaced if pin damage occurs. A target head adapter, which is specific to the device or family you are emulating, attaches to the TQSOCKET on one end, and to a controlled impedance flexible cable on the other end. The other end of the flex-cable attaches to the emulator system.
The specific part numbers for the MCU you are emulating can be found in our on-line development tool selector guide (SG173/D). Note that the purchase of a QFP target head adapter includes one TQPACK and one TQSOCKET. Additional TQPACKs and TQSOCKETs can be purchased for connecting with more than one target system. You can find the part numbers for additional TQPACKs and TQSOCKETs in the surface mount column of the selector guide. Refer to the following (a picture is worth a thousand words!):
1999Mar04
68HC05, 68HC08 CPU, Instructions What are the addressing modes of the 68HC05 and the 68HC08 and how are they used?
View the addressing mode matrix. 1999Mar04 68HC05, 68HC08 CPU, Instructions How could the SWI instruction be used in the 68HC05 during code development or in an application?
The SWI instruction can be used to make a specific block of code atomic, to do context saving, and to cause interrupt routine forcing or testing. Atomic code, which is defined in this context as a modularized block of code that is executed as a whole without interruption, is achieved because the SWI sets the I bit in the condition code register upon vectoring to the SWI service routine. Here a critical code area can be located that will execute completely before returning to the interrupted module.
If it is desirable to preserve the content of the registers before executing a block of code, then it may be easier to do this by using the SWI instead of calling a subroutine. In a subroutine, the A and X registers can be saved by storing them in variable locations in RAM, but there is no direct mechanism (without doing a bunch of bit testing) to save the condition code register. Instead, issuing an SWI automatically saves the context to the stack. Upon return (RTI) from this interrupt, all registers including the condition code register are restored.
Note about the 68HC08: In the 68HC08 there is an easy means of saving the condition code register by using the TPA instruction followed by PSHA. In fact, all of the registers could be preserved by pushing them onto the stack, but the SWI instruction does this automatically with a small exception. If using the SWI instruction or any other interrupt, it should be remembered that the H register is not preserved automatically. One must use PSHH at the beginning of the interrupt routine and PULH at the end to maintain the register's previous value.
Use of the SWI to save the context while executing a block of code can only be implemented for a single routine unless some selection method is used, such as passing a value (i.e., loaded into the accumulator) to the interrupt routine where a conditional branch can select the correct code to execute. Also note that using the C bit in the condition code register as a Boolean return value, as one might do in a normal subroutine, would not work for an interrupt routine as the condition code register is restored upon return from interrupt to its previous state when the interrupt occurred.
Another use of the SWI involves forcing the execution of another interrupt service routine. This can be especially useful during code testing when it is inconvenient to wait for a real interrupt to cause the execution of its service routine, or if there is a need to test the possible adverse effect of an interrupt during execution of critical code. By assigning the same vector for the SWI as the interrupt whose service routine is to be tested, the SWI instruction can be placed at any point in the program. This same method of forcing execution of an interrupt service routine may be useful in applications where a function needs to be executed both upon the occurrence of an interrupt as well as during normal program flow. Using the SWI to trigger its execution during normal program flow eliminates the need to maintain duplicate code. 1999Mar04 68HC05, 68HC08 CPU, Instructions What flags does the 68HC05 condition code register contain and how are they used? What instructions alter each of these flags?
The five flags of the 68HC05's condition code register, which is a subset of those found in the 68HC08, are half-carry (H), interrupt mask (I), negative (N), zero (Z) and carry/borrow (C). The half-carry flag is set whenever there is a carry from the low-order nibble (b3-b0) to the high-order nibble (b7-b4) after an execution of a BCD instruction. The only two instructions which can cause this flag to set are ADD and ADC (the MUL instruction automatically clears this flag, and the RTI overwrites the entire register). With the use of this bit, one can decimal-adjust the 8-bit value in the accumulator after execution of each of these two instructions (ADD or ADC) to preserve a BCD value. The following table shows what action would be taken to decimal correct based on the result of an add or add-with-carry operation, and the status of the C and H flags.
The I bit of the condition code register determines whether interrupts are serviced. It serves as a global interrupt mask and when this bit is set, then only the SWI will be serviced while the rest of the interrupts in the system become disabled. Instructions that affect this bit are CLI, RTI, SEI, STOP, SWI, and WAIT. The CLI, WAIT, and STOP clear this bit, while the SEI and SWI set it. The RTI overwrites the entire register. The CLI and the SEI are the two primary instructions to programmatically clear and set the I bit, respectively.
The N bit is set when the result of an operation sets bit 7 of the operand. Its primary use is with signed arithmetic and it signifies that the result of an operation is a negative number. It can also be used as a flag for normal bit testing of bit 7. Instructions which affect (set or clear) this bit are:
The clear (CLR) and the logical shift right (LSR) instructions always clear the N bit.
The Z bit of the condition code register is used extensively as a check to see if the result of an operation is zero. It is the flag commonly used in loop constructs to determine whether a loop should be repeated or exited. Instructions which affect this bit are exactly the same ones that affect the N bit, except that the CLR instruction always sets the Z bit and the result of an LSR may set or clear the Z bit.
The C bit of the condition code register is usually used to indicate a carry from an addition or a borrow as a result of a subtraction. It can also be set during bit shift operations, and there are specific instructions just to set or clear the carry bit. Instructions that affect the C bit are:
The clear carry (CLC) and multiply (MUL) always clear the C bit; the set carry (SEC) and complement instructions always set the C bit. 1999Mar04 68HC05, 68HC08 CPU, Instructions Which 68HC08 data manipulation instructions do not alter the condition code register?
It may be desirable to manipulate a register or memory without modifying the condition code register. This would be the case if a flag-setting instruction is intended to cause a later action like a conditional branch, but you want another data manipulation to take place in the meantime. It is worth noting which instructions may be used that modify a register or memory without altering any of the flags of the condition code register. They are:
This may not be an adequate set of instructions to perform the desired data manipulation. If this is the case, then use the TPA and then PSHA to save the condition code register for the later conditional branch, or use the SWI and perform the desired operation in the interrupt service routine. Upon return from interrupt, the condition code register will be restored. 1999Mar04 68HC05, 68HC08 CPU, Instructions All of the branch instructions, including branch always (BRA) and branch to subroutine (BSR), support only relative addressing. What addressing modes do the jump (JMP) and jump to subroutine (JSR) supp
Even though one must sacrifice code relocatability, the absolute addressing JMP and JSR instructions provide much more flexibility than their relative addressing counterparts. Each of these two instructions supports five addressing modes -- direct, extended, indexed, indexed with 8-bit offset, and indexed with 16-bit offset -- with extended addressing being by far the most commonly used mode for these instructions.
The use of direct addressing jumps is usually transparent to the programmer unless he is counting instruction bytes. This mode reduces the instruction length from three bytes for extended addressing to two bytes, since the jump destination is always in the first page of memory ($00-$FF).
Indexed addressing with no offset, an 8-bit offset, or a 16-bit offset is used to take different actions depending upon a data value or its location. For example, the following code would cause consecutive jumps to an array of different subroutines using the indexed with 16-bit offset addressing mode. This routine is a simplification and real code would probably contain selection criteria to determine which subroutines to execute depending upon certain existing conditions.
Even though one must sacrifice code relocatability, the absolute addressing JMP and JSR instructions provide much more flexibility than their relative addressing counterparts. Each of these two instructions supports five addressing modes -- direct, extended, indexed, indexed with 8-bit offset, and indexed with 16-bit offset -- with extended addressing being by far the most commonly used mode for these instructions.
The use of direct addressing jumps is usually transparent to the programmer unless he is counting instruction bytes. This mode reduces the instruction length from three bytes for extended addressing to two bytes, since the jump destination is always in the first page of memory ($00-$FF).
Indexed addressing with no offset, an 8-bit offset, or a 16-bit offset is used to take different actions depending upon a data value or its location. For example, the following code would cause consecutive jumps to an array of different subroutines using the indexed with 16-bit offset addressing mode. This routine is a simplification and real code would probably contain selection criteria to determine which subroutines to execute depending upon certain existing conditions. 1999Mar04 68HC05, 68HC08 CPU, Instructions Since the 68HC05 does not support user control of the stack, what can be done in software to provide stack functionality?
The stack is a data structure that could easily be implemented in a user program, which would perform some or all of the built-in features for using the stack in the 68HC08. The following is a simplified outline for a stack implementation, which could be modified or enhanced depending on specific requirements. This stack assumes an address decrement to get the next address to be accessed by the stack.
The PSHX instruction is used to push the contents of the X registers onto the stack. As a result of this operation, the stack pointer is decremented by 1. Often this instruction is accompanied by the PSHH instruction, which pushes the content of the H register onto the stack, to free the entire 16-bit index register for other use. In contrast to push instructions, the TXS instruction transfers the content of the index (H:X) register to the stack pointer, not the stack. The result of this operation causes the stack pointer to point to a location specified by the contents of the index register. Sometimes this is done when the index register is indexing through one set of data and it is desirable to index through another set of data at the same time. Here the stack pointer can be used as an index. However, great care should be taken when using the TXS instruction so as not to lose the content of the stack. 1999Mar04 68HC08 CPU, Instructions What is the V bit that has been added to the condition code register for the 68HC08 and how is it used?
The V bit is used primarily in signed arithmetic and is set when a twos complement overflow occurs as a result of an operation. An overflow, as used in this context, can occur after an addition or a subtraction. A general rule to determine whether the V bit gets set as a result of an addition is that if both operators are of the same sign, where a negative value always has bit 7 set, and the result is of the other sign, then the V bit will be set. It would not get set under any other conditions. For example, if $80 is added to $FF, then the result is $7F with the V bit set. If $01 is added to $7F, then the result is $80 and the V bit is set. For subtraction, the V bit is set if the result of the subtraction and the subtrahend is of the same sign and the minuend is of the other sign. In other words, the subtraction can be rearranged to form an addition, where the result is added to the value to the right of the minus sign and produces the value to the left of the minus sign. In this case, the previous rule for V bit setting for addition is followed.
This flag is useful when used in conjunction with the N bit, which gets set if the result of an operation is negative. Together, these two bits can indicate whether the result of an operation is really a positive value greater than 127 or a negative value. If the exclusive-ORing of these two bits results in a 0, then the final value is positive. If the result is 1 then the final value is negative. For example, if in the above example, $80 + $FF = $7F. The V bit gets set but the N bit is cleared, and the exclusive-OR of these two bits is 1 signifying a negative final value. But $7F is interpreted as +127 in signed arithmetic, which would be incorrect as -128 [$80] + (-1) [$FF] = -129. Another example would be subtracting $80 from $7F and getting $FF. Both V and N get set as a result of this operation which would exclusive-OR to produce a zero, signifying a positive value. It would be incorrect to interpret the result $FF as -1, as 127 - (-128)[$80] = 255 [$FF unsigned]. By knowing and using these two rules, you'll be sure to interpret signed arithmetic results correctly. 1999Mar04 68HC08 CPU, Instructions What new instructions have been implemented to support stack operations and control in the 68HC08? What existing instructions have been expanded to support stack operations?
Push instructions have been added which facilitate storage of the accumulator (PSHA), the X register (PSHX), and the H register (PSHH). Conversely, corresponding pull instructions (PULA, PULX, and PULH) have been added to load each of these registers with the value on the top of the stack. Direct transfer of register content between the stack pointer and the H:X register has also been added with the TSX and the TXS instructions.
All instructions that support indexed addressing mode for the (H:X) index register have been expanded to support one or both stack pointer addressing modes, except for JMP and JSR. This allows use of the instruction with the index relative to the content of the 16-bit stack pointer rather than the 16-bit H:X register. These instructions are: ADC*, ADD*, AND*, ASL, ASR, BIT*, CLR, CMP*, COM, CPX*, DBNZ, DEC, EOR*, INC, LDA*, LDX*, LSL, LSR, NEG, ORA*, ROL, ROR, SBC*, STA*, STX*, SUB* and TST. Also, the CBEQ instruction supports the Stack Pointer, 8-bit offset mode. Note that this instruction which has the form 'CBEQ offset, SP, reladr' does not automatically increment the stack pointer as it does the H:X register in its IX+ addressing mode.
*Supports both Stack Pointer, 8-bit offset (SP1) mode and Stack Pointer, 16-bit offset (SP2) mode, while the others support only Stack Pointer, 8-bit offset mode. 1999Mar04 68HC08 CPU, Instructions What instructions support the use of the 16-bit index (H:X) register in the 68HC08? Which of these support automatic incrementing of this register?
All instructions that support indexed addressing mode support the 16-bit H:X register for the index register. These instructions are: ADC, ADD, AND, ASL, ASR, BIT, CLR, CMP, COM, CPX, DBNZ, DEC, EOR, INC, JMP, JSR, LDA, LDX, LSL, LSR, NEG, ORA, ROL, ROR, SBC, STA, STX, SUB, and TST. In addition, there are two basic instructions which support the automatic incrementing of the H:X register. The CBEQ instruction supports the 16-bit Indexed, No or 8-bit Offset with Post Increment (IX1+) mode which post increments the H:X index register after the compare. Also, two of the four variations of the MOV instructions, Memory to Memory, 16-bit Indexed to Direct with Post Increment and Memory to Memory, Direct to 16-bit Indexed with Post Increment support the use of the H:X index register with post increment.
Other instructions which utilize this register pair are AIX (increments H:X by an immediate value), CPHX (compares H:X with 16-bit value in memory), LDHX (loads H:X), STHX (stores H:X), TSX (transfers stack pointer to H:X) and TXS (transfers H:X to stack pointer). Instructions that act on the H register separately are CLRH, PSHH and PULH. 1999Mar04 68HC05, 68HC08 CPU, Instructions Why can't I use BSET and BCLR instructions with write only registers?
BSET and BLCR are Read-Modify-Write instructions. Write-only registers will read back undefined data. Therefore, a Read-Modify-Write operation will read undefined data, modify it as appropriate, and then write it back to the register. Because the original data is undefined, the data written back will be undefined. 1999Mar04 68HC05 CPU, Instructions Why does the 68HC05 fetch an instruction but not execute it when using the CLI instruction?
The I bit is set after reset and is cleared by the CLI instruction. When there is a pending interrupt during or before the CLI instruction execution, the next instruction is fetched by the CPU but is not executed. The interrupt routine then runs. This has confused some people working with bus analyzers who are surprised to see the next instruction apparently run and then the interrupt routine run. 1999Mar04 68HC05, 68HC08 Exceptions, Memories What is the state of RAM after a cold versus warm reset? After exiting WAIT and STOP modes?
A cold reset, in this context, is defined as a low-to-high transition on the VDD line. The processor does nothing to RAM as part of its reset or start-up sequence. Therefore, the state of RAM is indeterminate after a cold reset, and the user should not depend on RAM data being retained or changed if power is removed for any length of time. On a warm reset, which can be caused by an external low-to-high transition on the RESET line, a COP time-out, an LVI reset*, or an illegal opcode/address reset, the state of RAM is retained as power has not been interrupted.
During transitions to (from) both WAIT and STOP modes, all registers, memory and I/O states remain unchanged. Therefore, the state of RAM is unaffected by use of these two low-power modes.
*Assumes that VDD has reduced to a level that causes the LVI reset, but has not dropped to a level that stops the device. See the documentation section on DC electrical specifications in the technical data book for the device being used. 1999Mar04 68HC05, 68HC08 Memories What is the minimum voltage needed on the micro ( VDD) to retain contents of RAM?
In units that have a low-voltage data-retention mode (i.e., C8A, J1A, J2, K1, P9, etc.), contents of RAM can be preserved at VDD voltages down to 2.0 V. To get into this mode, the reset line must be brought low (and kept low during this mode) and then VDD can be lowered to as low as 2.0 V. For controllers that do not have this mode, the only sure way of maintaining RAM content is to keep the device active either in standard operating mode or in a low-power mode (wait or stop). During active operation, the supply voltage of the device cannot be reduced below the specified VDD limits of the device, usually 4.5 V unless low voltage operation is supported. See the section on DC electrical specifications in the technical data book for your particular device. 1999Mar04 68HC05, 68HC08 Memories What is the SEC bit, why should I use it and how is it set?
The SEC, or Security, bit is located in the Option register and is usually implemented in the same type of memory as the program memory (i.e., EPROM, EEPROM). It is therefore non-volatile and its value remains intact during power down. Its purpose is to prevent unwanted examination of program memory by disabling entry into any mode other than user mode. This bit, which is set to turn security protection on, is programmed in the same manner and at the same time that the program array is programmed. 1999Mar04 68HC05, 68HC08 Memories Is there any benefit in not setting security?
It may be advantageous to get into another mode of operation other than user mode after the device is programmed. When this is the case and there is no concern about code secrecy, do not set security. For example, the Load-RAM-and-Execute capability of the bootloader mode is useful as a debugging or failure analysis tool for the micro or a peripheral circuit. A test program can be loaded into, and executed from, RAM without having to alter or change out the existing program code. If security is set, then entry into bootloader mode is disabled and one would not have the capability of loading a RAM routine unless it is built into the program code. 1999Mar04 68HC05 Memories What is PEP and how is it used?
PEP, or PEPROM, stands for Personality EPROM and is used to store user data or variables in non-volatile memory. This array has the advantage of being bit-addressable and is used primarily to store a serial or ID number that is unique to each individual unit. There are 64 bits of PEP in the 68HC705JJ7*, arranged as 8 bytes of 8 bits per byte. These bits are read serially by writing the bit location to be read into the PEPROM's Bit Select Register (PEBSR) and reading the state of the PEDATA bit of the PEPROM Status/Control Register (PESCR). To read a bit of the array, the byte is specified by assigning the binary value (000 to 111) of the byte to bits b5-b3 of the PEBSR, and then specifying the bit position (000 to 111) with bits b2-b0 of PEBSR. This completely identifies one and only one bit position of the array and its value can then be determined by reading PESCR's PEDATA bit.
Programming these bits is done with the same reference method where the bit position to be set is first specified in the PEBSR register. Then the PEPGM and CPEN bits of the PESCR are set and held for a specified delay time and then cleared again (see tEPGM in the Control Timing Specifications for the device). Erasing can be performed only on windowed devices with the use of an ultraviolet light. Consult the appropriate data manual for more detailed discussion on PEPROM.
*Also includes other family members such as JP7, SP7 and SJ7. 1999Mar04 68HC05 Memories What is PEEP and how is it used?
PEEP, or PEEPROM, stands for Personality EEPROM and is used to store user data or variables in non-volatile memory. This array has the advantage of being bit-addressable and is used primarily to store a serial or ID number that is unique to each individual unit. There are 128 bits of PEEP in the 68HC805K3 arranged as 16 bytes of 8 bits per byte. These bits are read serially by writing the bit location to be read into the PEEPROM's Bit Select Register (PEBSR) and reading the state of the PEDATA bit of the PEEPROM Status/Control Register (PESCR). To read a bit of the array, the byte is specified by assigning the binary value (0000 to 1111) of the byte to bits b6-b3 of the PEBSR, and then specifying the bit position (000 to 111) with bits b2-b0 of PEBSR. This completely identifies one and only one bit position of the array and its value can then be determined by reading PESCR's PEDATA bit.
Programming these bits is done with the same reference method where the bit position to be set is first specified in the PEBSR register. Then the PEPGM and CPEN bits of the PESCR are set and held for a specified delay time and then cleared again (see tEPGM in the Control Timing Specifications for the device). Erasing can be performed with the use of the PEBYTE (byte level) and PEBULK (entire array). Consult the appropriate data manual for more detailed discussion on PEEPROM. 1999Mar04 68HC05, 68HC08 Memories What is the erased state of an EPROM, OTPROM, EEPROM, and flash cell?
The erased state of EPROM, OTPROM and EEPROM varies from device to device. In most EPROM and OTPROM microcontrollers, an unprogrammed or erased state has value $00. This is true in the 68HC705B16N/B32, 68HC705C8A/C9A, 68HC705J1A, 68HC705JJ7 (including the PEP), 68HC705KJ1, 68HC705P6A, and others. An exception to this general rule is the 68HC705L16 which has an erased state of $FF.
The erased state of EEPROM in various devices is more complicated. In the 68HC705B16(N) and the 68HC705B32, while the EPROM has an erased state of $00, the small block of EEPROM in each of these devices has an erased state of $FF. The 68HC805P18 has two classifications of EEPROM memory, a 128-byte block of programming memory and a 8064-byte block of user EEPROM. The programming EEPROM's erased state is $FF while the user EEPROM's erased state is $00. In the 68HC805K3, the erased state for both the main EEPROM array and the personality EEPROM (PEEP) is $00.
In the A family of 68HC08's (i.e., 68HC908Az60, 68HC908AS60, etc.), the erased state of the large flash block(s) is $00, while the erased state of the smaller EEPROM block(s) is $FF. This is consistent with most flash arrays, where the erased state is $00. To be safe, check the data book to make sure of the erased state of memory for whatever device you are using.
In general, if an EEPROM array is the main user array for the device, then its erased state is $00. If the EEPROM is a smaller block of programming memory (not personality EPROM), then its erased state is $FF. This table summarizes memory types and erased states for the more popular Motorola devices. 1999Mar04 68HC05, 68HC08 Memories What is meant by the terms "unused", "unimplemented" and "reserved" in a memory map? Are these locations usable at all? Can the device be damaged or otherwise malfunction if something is written to thes"
Both "unused" and "unimplemented" bits or bytes of memory generally mean that they do not exist and therefore cannot be used. A "reserved" location, however, means that it contains data which may dynamically change based on a function put on the device for factory test or diagnostic purposes. Writing to, or reading from, any of these types of locations may not damage the part or cause the part to malfunction, but the user is urged not to use these locations. "
Both "unused" and "unimplemented" bits or bytes of memory generally mean that they do not exist and therefore cannot be used. A "reserved" location, however, means that it contains data which may dynamically change based on a function put on the device for factory test or diagnostic purposes. Writing to, or reading from, any of these types of locations may not damage the part or cause the part to malfunction, but the user is urged not to use these locations. 1999Mar04 68HC05, 68HC08 Memories I need a small amount of non-volatile memory for data storage. What are my options?
There is no bit to say there is a mismatch. Redundant mode works by combining the charge on the two cells with some analog circuitry. This combined charge is then used to determine if it is a 0 or 1. 1999Mar04 68HC908AZ60, 68HC908AZ32, 68HC08AZ32 Memories Software running on the 68HC908AZ60 contains two instructions to store data into CONFIG1 (address $1F) and CONFIG2 (address $FE01). Can we keep these two instructions in the code submitted for the ROM v
There is no problem with retaining writes to the Config Registers in code submitted for the ROM version of the 68HC908AZ60.
These registers are not implemented on the 68HC08AZ32 and have no effect.
There is no problem with retaining writes to the Config Registers in code submitted for the ROM version of the 68HC908AZ60.
These registers are not implemented on the 68HC08AZ32 and have no effect. 1999Mar04 68HC08AZ60, 68HC908AZ60 CPU, Instructions, Clocking Why did the monitor mode communication baud rates change on the 68HC908AZ60 masks 1J66D and 1J61D?
Symptom:
The original 68HC08 secure monitor could not reliably communicate with a PC serial port when the 68HC08 was clocked with a 4-, 8-, or 16- MHz crystal. The user was forced to use a 4.9152 MHz crystal to guarantee reliable operation. This crystal is not a popular choice with customers using the MSCAN module.
Solution:
Monitor Mode on 1J66D (68HC08AZ60) and 1J61D (68HC908AZ60) differs from previous mask sets in one area, baud rate. The next table shows the baud rates which are available for a range of crystals. The table lists the two baud rates the 68HC08 can produce using a given crystal, and the closest baud rate which a standard PC communication port can reliably generate. The generated baud rates were chosen so that it was still possible to communicate with the 68HC08 using 4.9152 MHZ and 4.194 MHz crystals.
Remarks:
An IBM-compatible PC communication port can generate required baud rates for all frequencies listed in the previous list. 1999Mar04
68HC08, 68HC908AZ60, 68HC908AZ32 J1850 What should I do with the BDLC pins when using 68HC(9)08AS to emulate the 68HC(9)08AB parts? There are two pins used in the BDLC module: BDRxD and BDTxD
BDRxD is the BDLC' s receive pin and, out of reset, is set as high input impedance. It is best to tie this pin low (via a low value resistor) to avoid the possibility of accidentally ' awakening' the BDLC module. This is also the best way to draw the least amount of current.
BDTxD is the BDLC' s transmit pin and as such is an output driven by the MCU. It is best to leave this floating rather than tying high or low.
Summary :
BDRxD = tie to VSS via a low value resistor
BDTxD = leave floating 1999Mar04
68H908GP20, 68HC08 Electrical Specification What are the estimated run IDDs of the 68HC908GP20 with and without each module?
Run IDD with all modules operating is approximately 27 mA @ VDD = 5.5 V, FBUS = 8 MHz.
A rough estimate as to where current is going is as follows:
| Module | IDD (mA) |
| None | 15 |
| SCI, SPI, Timer | <1 |
| A/D | 6 |
| PLL | 4-5 |
This PLL requires a reference clock of 16 to 100 kHz. The maximum divider value is 15, so the maximum external clock source you can use with the PLL is 1.5 MHz. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Clocking What is the expected start-up time for the 68HC908GP20/32 when being clocked by a 32.768 kHz crystal?
With a 32.768 kHz crystal, the expected power-on delay is 497 ms.
4064 * tcyc = 497 ms , where tcyc = 8192 Hz (32.768 kHz/4)
The PLL is on at reset, but the BCS (base clock select) is cleared, making the 32.768 kHz crystal the clock source for the bus. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Clocking What are the clock options for the 68HC908GP20/32?
There are only 2 options for clock source for the 68HC908GP20. Either a crystal in the range of 30-100 kHz or an external oscillator in the range of DC - 32.8 MHz (PLL disabled) or 30 kHz - 1.5 MHz (PLL enabled). The PLL can be used to bump up either of these two clock references to a resulting internal frequency up to 8.2 MHz @ VDD = 5 V (4.1 MHz @ VDD = 3.3 V). See section 7.4.6 of the 68HC908GP20 documentation for a procedure on how to program the PLL. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Clocking I want the PLL in the 68HC908GP20/32 to generate 2 MHz using a 32 kHz crystal. How do I do this and what problems should I look for?
There are some gotchas to consider for use of the PLL with a 32.768 kHz crystal.
A code segment follows:
;Assembler equates
| PCTL | EQU | $36 |
| PBWC | EQU | $37 |
| PMSH | EQU | $38 |
| PMSL | EQU | $39 |
| PMRS | EQU | $3A |
| PMDS | EQU | $3B |
| BCS | EQU | $04 |
| PLLON | EQU | $05 |
| AUTO | EQU | $07 |
-----------------------------------; Set it up
| BCLR | BCS,PCTL | ;Select external clock | |
| BCLR | PLLON,PCTL | ;Turn PLL off | |
| CLR | PCTL | ;Clear P and E | |
| MOV | #$1,PMDS | ||
| MOV | #$0,PMSH | ||
| MOV | #$F4,PMSL | ||
| MOV | #$D0,PMRS | ||
| LDA | PCTL |
--------------------------------------;Turn it on
| BSET | AUTO,PBWC | ;Automatic bandwidth control | |
| BSET | PLLON,PCTL | ;Turn PLL on | |
| BRCLR | LOCK,PBWC,* | ;Wait for lock | |
| BSET | BCS,PCTL | ;Select PLL output as base clock |
There is no such voltage vs. frequency curve. The specs in the GRS are given for VDD voltages of 3 V and 5 V (+/-10%). The acceptable range for bus frequency is given for each of these two voltage levels. Operation at other voltage levels and frequencies above those given is not specified.
There is no such voltage vs. frequency curve. The specs in the GRS are given for VDD voltages of 3 V and 5 V (+/-10%). The acceptable range for bus frequency is given for each of these two voltage levels. Operation at other voltage levels and frequencies above those given is not specified. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Clocking If the external clock is 10 MHz for the 68HC908GP20/32, then what is the internal bus frequency?
In user mode, the internal frequency of an 68HC08 is always the external frequency (CGMXCLK) or the PLL frequency (CGMVCLK) divided by 4. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Timer When using buffered PWM mode in the 68HC908GP20/32, is the second channel's pin available for digital I/O?
The TIM08 manual states that in buffered PWM mode the unused channel reverts to port control. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Timer We have a problem with setting a signal's duty cycle using unbuffered PWM in the 68HC908GP20/32. The duty cycle should be an 8-bit value (0-255) but at a value of 72/255 or more we get a 100% duty cycl
To obtain 100 kHz signal frequency, you are probably programming the modulo register (T1MODH/T1MODL) with $0048 (72 decimal). The CH1F bit will never get set for channel register values that are higher than the value in the modulo registers, because the timer counter can only take on values up to and including the value in the modulo registers. Therefore, if you are comparing the timer value to an always higher value in the channel registers, then a compare event (toggle, set or clear the output) will never occur and you'll see a 100% duty cycle.
To obtain 100 kHz signal frequency, you are probably programming the modulo register (T1MODH/T1MODL) with $0048 (72 decimal). The CH1F bit will never get set for channel register values that are higher than the value in the modulo registers, because the timer counter can only take on values up to and including the value in the modulo registers. Therefore, if you are comparing the timer value to an always higher value in the channel registers, then a compare event (toggle, set or clear the output) will never occur and you'll see a 100% duty cycle. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Serial Communication What is the base clock for the SCI in the 68HC908GP20/32? We will be using a 9.8304 Mhz crystal as the input to the chip. Isn't the BAUD rate selected using the internal bus frequency or is it the osci
The reference clock for the SCI can be either CGMXCLK or the internal bus clock, depending on the setting of the SCIBDSRC bit in CONFIG2. SCI baud rate is defined as (selected reference clock frequency) / (64 * PD * BD), where PD and BD are the prescaler divisor and the baud rate divisor, respectively. This allows a theoretical maximum baud rate at VDD = 5V to be 32.8 MHz / (64 * 1 * 1) = 512.5 kbps.
The reference clock for the SCI can be either CGMXCLK or the internal bus clock, depending on the setting of the SCIBDSRC bit in CONFIG2. SCI baud rate is defined as (selected reference clock frequency) / (64 * PD * BD), where PD and BD are the prescaler divisor and the baud rate divisor, respectively. This allows a theoretical maximum baud rate at VDD = 5V to be 32.8 MHz / (64 * 1 * 1) = 512.5 kbps. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Analog Can the A/D in the 68HC908GP20/32 have reference voltages at voltage levels other than VSS/ VDD?
Vrefh and Vrefl are set via the VDDad and BSSAd pins, respectively. These pins must be at the same voltage potential as VDD and VSS, respectively. 1999Mar04 68HC08, 68HC908GP20, 68HC908GP32, 68HC05GP32 Analog The Analog-to-Digital Converter section of the data book for the 68HC908GP20 says that the conversion process is monotonic and has no missing codes. But what is the accuracy in terms of the number bits
Section 23.13, page 391, of the Advanced Data Book, rev. 2.0, shows the ADC specifications. The ADC is accurate to (+/-) 1 LSB, provided appropriate bypassing is implemented.
Section 23.13, page 391, of the Advanced Data Book, rev. 2.0, shows the ADC specifications. The ADC is accurate to (+/-) 1 LSB, provided appropriate bypassing is implemented. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Memories Is the RAM in the 68HC908GP20/32 secured when security fails when entering monitor mode?
No. The only thing that is protected and can't be read is the FLASH ROM. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Memories When programming or erasing the flash memory in the 68HC908GP20/32, can the code which does the programming or erasing reside in another portion of flash memory or must it reside in RAM?
The process of programming a FLASH array requires that the entire array be put in a Write mode and therefore one cannot execute (read) from an array that is being programmed. Since the 68HC908GP20/32 has only a single array, program execution must occur out of RAM. By contrast, the 68HC908AZ60 has two arrays so one array can be programmed by code executed out of the other array. 1999Mar04 68HC908GP20, 68HC08 Memories Can the address space that has been unimplemented in the 68HC908GP20 be used (shows 40K unimplemented space in the memory map)?
No. The 68HC908GP20 does not have an external bus, so mapping an external peripheral into its address space is not possible. Incidentally, trying to execute from an address in an unimplemented area of memory will cause an illegal address reset. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Memories Can one program in-circuit in the 68HC908GP20/32 with a 32.768 kHz crystal and the PLL?
Yes. Blank parts can enter monitor mode with IRQ low, thereby automatically causing the PLL to generate a 2.4576 MHz internal frequency. This frequency will not only allow 9600 baud communication over PTA0, it will also generate an adequate (> 1.8 MHz) charge pump frequency to program FLASH.
For in-circuit reprogramming, it is up to the user's code to enable the PLL to generate an internal frequency of at least 2 MHz and one that will facilitate serial communication at a standard baud rate. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 General I/O Which I/O pins in the 68HC908GP20/32 are (or can be configured as) open collector?
The 68HC908GP20 does not have open-drain general I/O outputs available. The SPI output drivers have open-drain capabilities, but that is only with the SPI enabled (no digital output open-drain available). 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Misc., Memories What if I forget the security sequence in my 68HC908GP20/32? Is this device usable?
One can erase the FLASH after entering monitor mode and failing security by then loading a RAM routine that executes a bulk erase. A bulk erase is the only FLASH access operation that can be performed when security entry fails. The RAM routine should follow the bulk erase procedure outlined in the 68HC908GP20 documentation. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Misc., Memories What are the requirements of entering monitor mode in the 68HC908GP20/32?
There are two general scenarios when entering monitor mode: when there is VTST (~ VDD + 2V) applied to IRQ or when VDD or VSS is applied to IRQ. The first case needs to be done when the reset vector ($FFFE-$FFFF) is not blank but VTST can also be applied when the reset vector is blank.
When the reset vector is blank as in the case when the part is unprogrammed and the entire FLASH is blank, monitor mode can be entered with VTST, VDD or VSS applied to IRQ. If VTST is applied, port C settings are enforced to enter monitor mode. The port C requirements are C0 must be tied to VDD, C1 must be tied to VSS, and the state of C3 determines whether the internal frequency will be the external clock divided by 2 (C3 low) or the external clock divided by 4 (C3 high). If VDD is applied, then the internal frequency is the external (oscillator) frequency divided by 4, and the communication rate is the internal frequency divided by 256, or the external frequency divided by 1024. If VSS is applied to IRQ with the reset vector blank, then the PLL is automatically engaged. The PLL will set the internal frequency to 2.4576 MHz when the external clock (crystal or oscillator) is 32.768 kHz. Again the communication rate is the internal frequency divided by 256 - in this case 9600 bps. In either of these latter two situations, port C pins do not have to be set to any particular polarity and, in fact, port C3 has no effect on internal frequency.
If the reset vector is non-zero, as is the case when the part has already been programmed, then VTST must be applied to IRQ and the communication rate is the internal frequency divided by 256. The state of port C3 determines the internal frequency and the communication rate. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Misc., Memories What does the 68HC908GP20/32 do when I fail security? Can I reprogram the part if I don't know the security sequence?
After failing security, the monitor is still active and one can still execute the six monitor mode commands, which will allow one to download and execute a RAM routine. The FLASH array is still secured and cannot be read, however, it can be bulk erased. By performing a bulk erase in the RAM routine, one can clear the FLASH array and the part can be reprogrammed and re-used. 1999Mar04 68HC908GP20, 68HC908GP32, 68HC08 Misc., Memories After failing security in the 68HC908GP20/32, can I reset the part and try to pass security again?
Yes, but the reset must be a power-on reset, not just a pin reset. Incidently, indication of whether security entry is successful can be monitored by checking address $40, bit 6. If it is high, then security entry was satisfied 1999Mar04 68HC11, 68HC12 Clocking How do I lay out my crystal and get a reliable E clock out of the microcontroller?
As in all crystal oscillator designs, all leads should be kept as short as possible. It is also good practice to route VSS paths as shown in Section 2.2.3 of the MC68HC11 Reference Manual. 1999Mar04 68HC11, 68HC12 Clocking Why is my crystal starting up sporatically?
If your crystal circuitry is not starting reliably, it's probably due to added capacitance on C1 and C2. Motorola's recommended value given in chapter 2 of the 68HC11 Reference Manual (M68HC11RM/AD), is between 5 pF and 25 pF. If the PCB's stray capacitance is higher than about 15 pF, The crystal total impedance can be marginal and not provide enough gain for the circuit to start. A good fix is to reduce the value from the load capacitors. 1999Mar04 68HC11, 68HC12 Clocking Why is my crystal specified at 8 MHz, running at higher speeds?
When a crystal's impedance is not set up correctly, and the crystal maximum specification is violated, the crystal can oscillate at a higher frequency. When crystals are overdriven they are capable of oscillating at a higher speed or sometimes at second harmonics. Although the word characterizing sometimes sounds difficult, usually varying the feedback resistor can diminish current exposure to the crystal.
Reference 68HC11 application note AN1706/D. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12 Clocking What is the difference between AT-cut and AT-strip crystals?
The difference between these crystals is the angle in which they were cut. AT-strip crystals are thin, rectangular pieces of quartz. AT-strip pieces are much smaller than AT-cut pieces, therefore drawing less current to oscillate.
Reference 68HC11 application note AN1706/D. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12 Clocking What is the difference between crystals and resonators?
Resonators are lower-cost, less exact when oscillating than crystals.
Reference 68HC11 application note AN1706/D 1999Mar04 68HC12 Clocking Is there a problem using Murata resonators with 68HC912D60 and 68HC912DG128? Murata has found some problems in their testing. Our analysis so far:
1999Mar04 68HC12 Clocking, Timer In queue mode, if the input capture is polled, is it possible that the pulse accumulator value will not be the corresponding value to what has been read from the input capture register? Symptom: Yes. In queue mode, if the input capture is polled, it is possible that the pulse accumulator value will not be the corresponding value to what has been read from the input capture register. Usually after polling, the code will:
read input capture register
read input capture holding register
Read pulse accumulator holding register
If a pulse is received in between reading the input capture register and input capture holding register then the pulse accumulator holding register will read one pulse too many. (e.g. if a read of the input capture register has a timer value for the ninth pulse because another pulse was received, the pulse accumulator holding register will read 10.)
Explanation:
Reading the input capture holding register latches the pulse accumulator register to the pulse accumulator holding register. This will be mismatched due to the next pulse being received.
Solution:
The software should:
read input capture register and store in a temporary variable
read input capture holding register
read input capture register and compare with temporary variable
if these values are equal then
read pulse accumulator holding register
else continue reading and comparing until they are equal
Remarks:
This is not a malfunction the device was designed to function in this way. 1999Mar04
68HC12 Analog If the 68HC12 Analog-to-Digital converter is a 10-bit A/D, why is it only specified at eight bits?
Currently Motorola has allocated testers that test an A/D to 8-bit resolution that being a limiting factor for testing current product. Testers are being qualified to test the 68HC12's A/D at 10-bit resolution. However, if users want to use 10-bit mode, refer to the 68HC12 A/D initialization code FAQ. 1999Mar04 68HC12 Analog What is the fastest speed of acquisition for the A/D on the 68HC12 microcontroller?
The oscillator frequency is divided by two to generate E clock and P clock. P clock then feeds into the ATD prescalers and then another divide-by-two stage. Therefore, when the user sets the A/D prescaler bits to zeros, the P clock frequency is divided by two. When the micro is running at 8 MHz E clock, the ATD clock becomes 2 MHz. 1999Mar04 68HC12 Analog What is the definition for the Nyquist criteria when sampling signals?
2 times the maximum frequency of a signal, including noise. 1999Mar04 68HC12 Analog How do I initialize the A/D to start one acquisition?
INIT_AD1999Mar04 68HC12 Analog In the technical summary for the 68HC12, it states that after turning the ADPU bit on, the code must wait for a period of time to allow the analog circuits to stabilize. What is that time defined to be?A delay of 10 us will be sufficient. A delay of 10 us will be sufficient. 1999Mar04 68HC12 Analog How do I read the 68HC12 A/D result registers?
LDAA #$80 STAA ATDCTL2 ;Power up the A/D module JSR delay_ad ;wait to stabilize LDAA #$70 STAA ATDCTL5 ;run in normal mode LDAA #$81 ;enable 10 bit A/D STAA ATDCTL4 ;Fastest acquisition mode RTS
Users are welcome to use the following routine.
CONVERT1999Mar04 68HC12 Analog How can I send with interrupts enabled on the 68HC12 ADC?
PSHA LDAA #$FF ;start acquisition STAA ATDSTAT STAA ATDSTAT WAIT_AD0
LDAA ATDSTAT ANDA #$01 CMPA #$01 BNE WAIT_AD0 ;wait_ad LDAB ADR0H ;Fetched 8 bits only LDD ADR0H ;Fetched 10 bits. STD 0,Y ;IY is a pointer to data array PULA ;Restore REG A RTS
This handler and main routine will help you start. The main program is responsible for monitoring "COMP_FLAG" and using the data properly.
ATOD_HANDLER1999Mar04 68HC12 Analog What can we guarantee for the total accuracy of the 68HC912DG128 10-bit ADC?
CPY #data+512 ;Check data overrun. BEQ SETFLAG ;by comparing the pointer by 512 ;assurance to 256 points is established. ;and no more conversions will be taken LDAA ATDSTAT,X ;check CCF0 ANDA #$01 ;mask value in AN0 CMPA #$01 ;check proper value BNE OUTRTI ;---if program gets here channel one is the interrupt--- LDD ADR0H ;Fetch A/D 10-bit value STY 0,Y ;Store into DATA array INY ;walk the pointer by one INY ;walk the pointer by one LDAA #$ff ;start one more STAA ATDSTAT,X BRA OUTRTI SETFLAG
LDAA #1 STAA COMP_FLAG ;when low acquisition just started ;Announce completion to main OUTRTI
RTI
Currently there is no 10-bit test carried out on the 912DG128. The 8-bit A2D tests are carried out for 1 lsb accuracy at 8-bit resolution (input of (VRH-VRL)/2 + (VRH-VRL)/512) with the acceptable results being $80 or $81. 1999Mar04 68HC12 Timer What's the fastest possible output compare I can generate on the 68HC12?
You can get up to 4 MHz on an output compare channel on the 68HC12 devices, if you utilize the automatic timer counter reset feature of this timer module.
The following is a code segment which sets up OC0 to toggle and OC7 to reset the timer counter automatically when the TC7 value is reached.
1999Mar04 68HC12 Serial Communication How can I compute the SCI baud rate on the 68HC12?
clr PORTT ldaa #$01 staa DDRT bset TIOS,$81 ldaa #$01 ;Use Channel 0 staa OC7M staa OC7D ldaa #10010000Q ;Fast flag clear - unneeded here staa TSCR ;Enables Timer ldaa #$00 staa TCTL1 ldaa #$01 staa TCTL2 ;Set channel 1 to toggle ldaa #00000000Q ;What channels can cause IRQ staa TMSK1 ; (none here) ldaa #$08 staa TMSK2 ldd #$0000 std TC0 ldd #$0002 std TC7 With the above code segment (and an 8 MHz E-clock), the following values can be achieved:
TC0 Value TC7 Value Frequency at OC0 $02 $04 1.6 MHz $02 $03 2.0 MHz (75% duty cycle) $01 $03 2.0 MHz (50% duty cycle) $00 $03 2.0 MHz (25% duty cycle) $01 $02 2.6 MHz (66% duty cycle) $00 $02 2.6 MHz (33% duty cycle) $00 $01 4 MHz (50% duty cycle)
The SCI baud rate is based on the M Clock in the 68HC812A4 device, and P Clock in the 68HC12B32 device. Both of these clocks are the same frequency as the E Clock (crystal frequency/2). The following formula can be used to calculate baud rates:
Desired Baud Rate = MCLOCK / 16 * BR
Where BR is the value written to bits SBR[12:0] in the baud rate control registers. There is a table in the technical summaries for each device which shows the BR values for standard baud rates. 1999Mar04 68HC12 Serial Communication What is the maximum transmission rate for the SCI on the 68HC12?
If you compute SCIbaud = MCLOCK / 16 * BR where BR = 1 and Eclock = 8MHz, gives a maximum transfer rate of 500 K. Theoretically this is the fastest transfer rate. 1999Mar04 68HC12 Serial Communication How do I initialize the 68HC12 SCI to poll data?
Use the following steps.
INIT_SCI1999Mar04 68HC12 Serial Communication How do I send a byte from the 68HC12 SCI module?
MOVB #$26,SC0BDL ;Set the Baud Rate MOVB #$00,SC0CR1 MOVB #$0C,SC0CR2 LDAA #$0C STAA SC0CR2 RTS
The following routine can be used to send 256 points stored in the array DATA to the SCI.
TRANSMIT1999Mar04 68HC12 Serial Communication What is maximum transmission rate for the SPI on 68HC12 microcontrollers?
TR0LDX
#DATA
BRCLR SCOSR2,$80,TR0 ;Monitor the Transmit empty flag MOVB 1,X,SC0DRL ;Move data to the SCI register INX CPX #DATA+256 BNE TR0 ;If data is collected exit RTS
The E or P clock (same rate) is the basis for the SPI clock. The divider for this rate is a maximum of 8-bits (256). The minimum divider is 2, resulting in a maximum SPI clock of 4 MHz for an 8 MHz E clock rate. 1999Mar04 68HC12 Memories How many write/erase cycles are there on the Flash modules of the 68HC12?
The Flash EEPROM on 68HC912 products are guaranteed for 100 write/erase cycles. 1999Mar04 68HC12 Memories What is the recommended programming voltage for the 68HC912 Flash EEPROM?
The maximum programming voltage (VFP) allowed for the Flash module :
For masks 1H91F, 3H91F is 11.4 - 11.8 Volts.
Higher voltages can cause premature failure of the Flash module.
For all other masks, use 11.4 - 12.6 V (12 V +-5%)
See the errata for the particular mask set you are using. 1999Mar04 68HC912B32, 68HC12 Memories How do I program/erase the 68HC912 Flash module?
The basic procedures for programming and erasing the Flash module are outlined in Section 7 FLASH EEPROM of the MC68HC912B32 Technical Summary, as well as engineering bulletin 183 (EB183/D). EB183 contains example assembly code that programs and erases the Flash. Both documents contain flow charts that describe the procedures, as well as descriptions of all the Flash EEPROM control registers.
Reference 68HC12 engineering bulletin EB183/D. 1999Mar04 68HC12 Memories I am using an MC68HC12B32EVB and I have applied VFP to the board, but the Flash is not programmed/erased. Why?
Several things might be happening. Make sure that the jumper on W7 is applied to pins 1 and 2. This connects the VFP pin on the microcontroller to the VPP input header W8 on the board.
If that is not the problem, and you are using SDBUG12 with the Serial Debug Interface, try resetting the part to see if the proper values are displayed. There are a few glitches in some versions of this software which can cause the wrong values to be displayed on the screen when displaying the Flash memory and manipulating the Flash control registers. Resetting the part will cause SDBUG12 to reload all values for display, thus clearing up the problem. 1999Mar04 68HC12 Memories Where can I find information to program the 68HC12 EEPROM/EPROM?
The algorithms are found in technical summaries or data books for each individual device. 1999Mar04 68HC12 Memories What is the maximum amount of writes for the 68HC12 EEPROM?
Guaranteed to 10,000 writes across rated temperature range (not just room temp) and 10 years retention. 1999Mar04 68HC12 Memories What is the time required to erase the EEPROM on a 68HC12 device?
The typical time for a bulk erase is 10 ms. 1999Mar04 68HC12 Memories How do I erase the 68HC12 EEPROM?
Try this procedure:
BULK_ERASE1999Mar04 68HC12 Memories How can I prepare to program/erase 68HC12 EEPROM?
MOVB #$06,EEPROG ;Set the bulk Erase ;EELAT=ERASE=1, ROW=BYTE=0 LDY #$1000 MOVB #$AA, 0, Y MOVB #$07, EEPROG ;Turn on programming voltage EEPGM BSR DELAY ;write it for 10 mS BCLR EEPROG, #$01 ;Turn on programming voltage EEPG BCLR EEPROG, #$02 ;Clear EE latch, EELAT=0, Enables RTS ;Return from subroutine
Try this code:
To INITIALIZE:1999Mar04 68HC12 Memories How do I program 68HC12 EEPROM?
INIT_EE MOVB #$BF,EEPROT ;EEPROM available from ;$1000-$17FF (Blocksize=2048 Bytes) MOVB #$FE,EEMCR ;Lock Protect bits(write) and select system clock RTS
Try using the following procedure.
PROGRAM1999Mar04 68HC12 Memories What can I do to protect the integrity of data residing on 68HC12 EEPROM modules?
LDX #NAME PROGBYTE
LDAA 0,X+ BEQ EXIT MOVB #$02,EEPROG ;Set EELAT bit in EEPROG register STAA 0,Y+ ; Store data byte to LATCH, increment Y MOVB #$03,EEPROG ; Turn programming voltage on, EEPGM=1 BSR DELAY ;10mSeconds BCLR EEPROG,#$01 ; Turning off programming voltage EEPGM=0 BCLR EEPROG,#$02 ; Clear EE Latch, EELAT=0, Enables Read BRA PROGBYTE EXIT
RTS
The biggest enemy of an EEPROM cell is the introduction of a voltage transient that violates the electrical specification of the microcontroller. A transient in the negative domain can cause damage to the cell to the point of rendering the cell useless. 1999Mar04 68HC12 Memories Why does the technical summary say that programming 68HC12 EEPROM with interrupts enabled is not a good idea?
It only warns programmers to always stay within 10 msecs of programming time. Overstressing an EEPROM cell can result in permanent damage. 1999Mar04 68HC12 Memories Can you execute code in 68HC912D60 Flash memory 2 at the same time you are programming in memory 1, M1?
Yes. In the 68HC912D60 it is possible to program one flash block while running the flash programming algorithm from the other block. 1999Mar04 68HC912B32, 68HC12 Memories What code can a customer use to program 68HC12 flash blocks thru the SCI?
Refer to 68HC12 application note AN1718/D - a Serial Bootloader for Reprogramming the MC68HC912B32 Flash EEPROM 1999Mar04 68HC12 Memories If I want to protect my Boot loader for CAN in the 68HC912D60's M1 (for instance), can I then protect in smaller areas than 16 K? The bootloader is only about 1.2 K, so it would be a waste of space. Ot
Two protected blocks are in the 68HC912D60, one in each of the flash modules, but they are both 8 K, so the smallest protected block size is 8 K. Depending on the system requirements, it might be possible to use the 1K EEprom, which has configurable protected block sizes down to 64 bytes.
Two protected blocks are in the 68HC912D60, one in each of the flash modules, but they are both 8 K, so the smallest protected block size is 8 K. Depending on the system requirements, it might be possible to use the 1K EEprom, which has configurable protected block sizes down to 64 bytes. 1999Mar04 68HC12 Development tools, Memories Why does Prog12s not work with the 68HC912D60 mask set F73K?
It is not possible to program the 912D60, F73K mask set EEprom locations with P&E's Prog12s program, but there is no problem with the F68K mask sets.
The BDM lockout feature that was added to the F73K mask sets is controlled from bits in the EEprom control registers. The existing .12p file enables the BDM lockout feature as part of its initialization routine, which immediately locks out the BDM interface.
Solution:
Using a text editor modify the existing .
Change these lines,
| WRITE_BYTE=60/000000F0/ | ;Clear eemcr, prot. off |
| WRITE_BYTE=00/000000F1/ | ;Clear eeprot, turn off block protects |
To:
| WRITE_BYTE=F8/000000F0/ | ;Clear eemcr, prot. off, disable BDM lockout |
| WRITE_BYTE=80/000000F1/ | ;Clear eeprot, turn off block protects, |
| ;protect shadow register |
Remarks:
Having manually edited the .12p file, when attempting to load the modified file into Prog12s, a checksum warning will be issued, but can be ignored. 1999Mar04 68HC12 Exceptions Why do I get a reset vector fetch when the COP Interrupt ($FFFA, $FFFB) is enabled?
The primary possibility is that an external device pulls down the reset pin for a long time on any reset. A common way this happens is that the customer has put an external capacitor on the reset pin.
From the Technical Summary:
The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than eight E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for about 16 E-clock cycles, then released. Eight E-clock cycles later, it is sampled. If the pin is still held low, the CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either the COP system or the clock monitor.
(end of technical summary quote)
Solution:
To prevent a COP or clock monitor reset from being detected as an external reset, the reset pin must not be held low by external circuitry during a COP or Clock Monitor reset sequence. An external RC power-up delay circuit on the reset pin is not recommended. Circuit charge time can cause the MCU to misinterpret the type of reset that has occurred.
Conversely, for a true external reset to be properly identified, the reset pin must be held low by this reset circuitry for at least 32 cycles. 1999Mar04 68HC12 Exceptions Why would software interrupts occur untimely when output compare interrupts occur on 68HC12s?
Symptom;
In our program, the different interrupts are enabled in the output compare interrupt (CLI instruction). If two output compare interrupts are running independently, a software interrupt (IT_SWI) has occurred without a SWI instruction. As can be seen in the explanation, the TMSK1 register is cleared just before the I bit of the CCR. If a "NOP" is implemented between TMSK1 = 0x00 and CLI() instructions, the problem disappears and the software interrupt doesn't occur.
Explanation:
A more general statement of the conditions that cause this to occur is that the source of a previous interrupt is cleared in one instruction and the next instruction is the CLI to re-enable interrupts.
Clearing of the source of the old interrupt occurs on the last cycle of the instruction. (See the cycle by cycle instruction documentation in the CPU12 Reference Manual, CPU12RM/AD). The CLI is a one cycle instruction. The delays to clear the logic of the old interrupt take longer than the CLI processing. (Interrupts are enabled faster than the old source disappears.) The CPU immediately starts a new interrupt process, but when it reaches the point to determine the source, it has now been cleared. The CPU does not know where the interrupt came from and has no pending interrupts, so it takes the default vector which has been defined as SWI.
Solution:
Place a NOP instruction between the interrupt source clear operation and CLI instruction
Example code:
Root cause fix:
This operation will not be changed in current 68HC12 (UDR) parts. 1999Mar04
68HC12 J1850 Can the BDLC generate interrupts?
Yes, the BDLC generates an interrupt. The BDLC state table records the current state into the BSVR register. The user's interrupt handler should read the BSVR and vector off. 1999Mar04 68HC12 J1850 What is the maximum speed on the 68HC12 BDLC?
The BDLC can be placed in what's called a 4x mode and is set to run at a maximum speed of 41.6 kbps. This currently only works for receiving messages, not transmitting them. 1999Mar04 68HC12 J1850 How do I read a 1 on the J1850 bus?
The BDLC is variable pulse width protocol and active to passive transitions and vise versa represent a bit. For more information, please refer to the BDLC Technical Reference Manual, BDLCRM/AD. 1999Mar04 68HC12 J1850 Why do I get a BDLC invalid symbol if I do not send within 370 us?
In older mask sets, like 1H91F, writes to the BDR must be within 370 us or the BDLC state machine will generate an Invalid Symbol. The state machine on the 9H91F should change this condition to not care about the time delay between bytes. 1999Mar04 68HC12 J1850 How does the BDLC start up from power up? The BDLC starts by generating an End Of Frame (EOF) condition. 1999Mar04 68HC12 J1850 How do I get the state table on the BDLC to start sending bytes?
Your program should have an executive responsible for updating the transmit buffer. After the buffer is filled, it is useful to send the first byte and the BDLC will generate the correct sequence of interrupts with BSVR values set to TDRE. This sequence will send the entire buffer provided that the tdre_handler is designed to write all the bytes to the BDR. 1999Mar04 68HC12 J1850 If my application has glitches, how does the BDLC handle it?
If any application generates a glitch into the bus and it is interpreted a short within the Start Of Frame by the BDLC can cause the BDLC to generate a pulse train. The fix is to include the following piece of code on invalid_handler.
serve7:
1999Mar04 68HC05, 68HC08, 68HC12, 68HC16, 68300, MCORE, MPC500 Misc. How do I get my questions answered?
inc inv_int clr status bset bcr2,y,$20 ; Setting 4X mode. bset portp,y,$20 ;Set PP5 for delay characterization jsr Delay ;Delay 50 to 60 uSec. bclr portp,y,$20 ; clear PP5 bclr bcr2,y,$20 ;Clear the 4X mode rti
1. Search through these FAQs to see if you can answer your questions.
2. Read documentation, such as technical data books, application notes, engineering bulletins, and the like. Most of the questions that we receive can be answered by careful examination of documentation. All these documents can be accessed at the Microcontroller Literature Web Site.
Okay, I've done all that, but I still don't have an answer!
The next step depends upon how and where you got your Motorola products. If you bought your parts through one of our parts distributors such as Arrow, Future, FAI, Avnet, EBV, or Wyle, then your next step is to contact a Field Applications Engineer (FAE) with that distributor. They are trained by Motorola at regularly held training sessions and should be able to solve your problem. If they don't know how to solve your problem, they have contacts within Motorola to help them get answers to you quickly and effectively.
If you buy directly from Motorola (few customers do, as it isn't cost effective without buying in very high volumes), you should contact your salesperson and they can assist you in locating a Motorola FAE.
What to know when contacting an FAE:
See next question!
If none of the above works, Motorola has a customer support hotline. The Technical Customer Focus Center (TCFC) can be reached at 1-800-521-6274. Calls placed to the TCFC are answered by Motorola support staff and are logged into an internal database. If needed, these calls are routed to the appropriate specialists within Motorola by the support staff
DO NOT CALL THE TCFC IF YOU ALREADY CONTACTED AN FAE!!!
This will only slow down the process, as many times these issues end up being routed to the same engineer within the plant from different sources. This increases the apparent workload and slows the engineer down. Please help us to serve you better by not placing multiple calls through multiple channels. Thank you!
What should I know/have available when I contact an FAE?
Other items which might be useful (so have them available):
1999Mar04
68HC11 CPU Where do I find a typical schematics for the 68HC11 in bootstrap mode?
The typical circuit can found on the M68HC11PCBUG11 User's Manual, M68PCBUG11/D in appendix A. However, to setup up the part in its simplest form, MODA/B are tied to ground and IRQ and XIRQ are pulled up through a 4.7 kOhm resistors. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16 Timer How can I generate a software delay with an Output Compare?
By enabling an Output Compare and each time the program executes the interrupt handler and offset value is added to TCNT and stored to the respective TOCX. 1999Mar04 68HC11 Timer Are there any documents on PWMs with 68HC11s?
Yes
Refer to engineering bulletin EB192/D (PWM_tutorial_for_K,KA,KW,P_and_PH_series) 1999Mar04 68HC11 Serial communication Is there a 68HC11 Family member that has an IIC module?
No. 1999Mar04 68HC11 Serial communication Can I interface an SPI device to a IIC device?
Yes, an article has been written that illustrates how to implement IIC with an SPI device. The article can found in EDN February 18, 1988, and the article Serial techniques expand your options for uC peripherals was written by Naji Naufel. 1999Mar04 68HC11 Serial communication What is the maximum transmission rate for the SPI on the 68HC11E Family of micro controllers?
On the 68HC11 Family, it is usually half the bus speed. 1999Mar04 68HC11 Serial communication Can I use the SPI as a master without the slave select line?
Yes. CPHA must be set to one to operate the SPI without a Slave Select. 1999Mar04 68HC11 Serial communication How many SPIs does the 68HC11 have?
Typically, the 68HC11 Family has one SPI port. 1999Mar04 68HC11 Serial communication How many modes does the SPI have on the 68HC11s?
Typically, the 68HC11 Family has two modes with a the capability to change clock polarity. 1999Mar04 68HC11 Serial communication Where can I read more about the SPI on the 68HC11?
Refer to section 8 of the 68HC11 Reference Manual, M68HC11RM/AD. 1999Mar04 68HC11 Serial communication What is maximum transmission rate for the SCI on the 68HC11 E series?
At 4 MHz, when all control bits are cleared on the BAUD rate register, the maximum transfer rate is 230,000. 1999Mar04 68HC11 Serial communication What is maximum transmission rate for the SCI on the 68HC11K Family?
If you compute:
SCIbaud = XTAL / 2 * 16 * BRwhere BR = 1 and Eclock = 4MHz.
This gives a maximum transfer rate of 500 K. 1999Mar04 68HC11 Serial communication What kind of level shifter should I use when using the 68HC11 SCI?
A level shifter commonly used in development tools is the MC145407P. 1999Mar04 68HC11 Serial communication Where can I learn about the SCI ports on the 68HC11s?
Refer to section 9 of the 68HC11 Reference Manual, M68HC11RM/AD. 1999Mar04 68HC11 Analog What is an Analog-to-Digital converter (ADC)?
An analog-to-digital converter is a device used to read a voltage from an infinitely variable (analog) voltage source and convert that voltage to the closest digital equivalent. An 8-bit ADC, such as those found in the 68HC11 Family, can convert an analog voltage to any one of 28 (256) discrete digital values. 1999Mar04 68HC11 Analog How do I determine the precision of a 68HC11 ADC?
In the 68HC11 Family of microcontrollers, precision is:
( VOLtage reference high) - ( VOLtage reference low)/ VDD 1999Mar04 68HC11 Analog What is the accuracy of the 68HC11 ADC?
1/-1LSB @ 2MHz
This assumes that VDD is 5 V. 1 LSB would be measured as 1/256v * Full-scale voltage reading (ideally, 5 V), which would be 0.01953 V (19.5 mV). 1999Mar04 68HC11 Analog Where can I read about the ADC module on the 68HC11s?
Refer to chapter 12 of the 68HC11 Reference Manual, M68HC11RM/AD. 1999Mar04 68HC11 Analog What is the fastest speed of acquisition for the ADC on the 68HC11 microcontroller?
It takes 32 E clock cycles for the Conversion Completion Flag (CCF) to set. Once the CCF flag is set, a complete conversion has taken place and the user program can read the result registers.
Refer to application note AN997/D. 1999Mar04 68HC11 Analog What design considerations should I take when using the 68HC11 ADC? VOLtage references should be extremely clean. Any voltage fluctuation can cause the ADC to give the wrong digital value. The 68HC11's environment must be protected from electromagnetic interference. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16 Analog How can I get rid of unwanted noise in my ADC reference pins?
The highest susceptibility of the converter to supply noise occurs in the last 30 nanoseconds (approximately) in the sample period ( 6 microseconds) of a conversion, which takes 16 microseconds at a 2.1 MHz bus frequency. Any disturbance to the ADC during this 30 nanosecond window is capable of causing an error. The most common source that disturbs the ADC are: supply noise generated internally by output buffers switching capacitive loads, especially in expanded/multiplexed operating mode. Decoupling for expanded mode is recommended and a capacitance should be applied at 1 uF paralleled with .01 uf. In single mode 0.1 uF is sufficient. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16 Analog How does a heavy switching application environment affect my accuracy?
Unfortunately, heavy switching will affect the voltage reference applied to the ADC, and accuracy and precision of the ADC module are a function of the reference voltage. Proper decoupling is recommended. 1999Mar04 68HC11 Memories Where can I find the routines/algorithms to program the 68HC11 EPROM?
Users can find the algorithms listed in the technical data for the series in use. 1999Mar04 68HC11 Memories How long does it take to erase 68HC11 EPROM?
If it is a windowed device, one can expose the device to UV for about 30 minutes or so to erase the memory. On an OTP (one time programmable) part, data is retained for many years and cannot be erased with UV light (no window!). 1999Mar04 68HC11 Memories Can I use the so-called PROG mode on 68HC11s?
NO. Motorola discourages customers from using mode. If you purchase a programmer, you should find out if the programmer uses the bootstrap mode to program the microcontrollers. 1999Mar04 68HC11 Memories What can I do to protect the 68HC11 EPROM array?
In an OTP device, the part does not have a window with which to erase the EPROM array. This prevents data loss due to UV light exposure. In a windowed part, you should always cover the window with a label or piece of tape (anti-static tape!) to prevent UV light from erasing the EPROM. 1999Mar04 68HC11 Memories, Development Tools Can I program the EPROM with a 68HC11EVBU2 or EVBU?
Yes, if you modify the board to provide 12 Volts on VPP.
Engineering bulletins:
EB296/D (HC711E9_Devices_with_PCbug11_and_EVBU)
EB298/D (Programming_BUFFALO_into_a_HC711E9_device_on_an_EVBU 1999Mar04 68HC11 Memories What is the maximum amount of writes for 68HC11 EEPROM?
Guaranteed to 10000 writes across rated temperature range (not just room temperature) and 10 years data retention. 1999Mar04 68HC11 Memories What is the time required to erase the EEPROM on 68HC711E9 devices?
The typical time for a bulk erase is 10 ms. 1999Mar04 68HC11 Memories What can I do to protect the integrity of data residing on an EEPROM module?
The biggest enemy of an EEPROM cell is the introduction of a transient that violates the electrical specification of the microcontroller. A transient in the negative domain can cause damage to the cell to the point of rendering the cell useless. 1999Mar04 68HC11 Exceptions Should I meet the RESET requirements for RESET and POR on the 68HC11/12 Families?
A microcontroller is a highly sensitive state table. At reset it expects a set of signal conditions as an input to get into the correct mode of execution. These conditions, MODA and MODB, are set during RESET. If the timing on these conditions is not met properly because of random spikes either below or above the rails the following symptoms will be experienced when running your application:
Yes.
Refer to Engineering Bulletin EB413/D (How_to_Configure_HC11_Reset_Pin). 1999Mar04 68HC11 Misc., Memories How do I program the CONFIG register on 68HC11s?
The CONFIG register can be programmed in all MODES. The CONFIG register one can build a circuit placing the 68HC11 in bootstrap mode and use PCBUG11 to of the MCU. The contents of the EEPROM byte are transferred into working latches during reset. In normal modes, changes to the CONFIG register do not affect operation of the MCU until the part is subjected to a RESET sequence. For a specific family of microcontrollers, CONFIG register programming routines are found in the technical data documentation. The part number is usually MC68HC11X/D, where X represents the family series.
For more documentation on the subject the following links are provided.
Refer to appliciation notes AN997/D and M68HC11CFG/D. 1999Mar04 68HC11 Misc., Memories What tools are needed to program the CONFIG register?
The CONFIG register can be programmed with the SPGMR11 under PROG11, or one can build a circuit placing the 68HC11 in bootstrap mode and using PCBUG11 to program the CONFIG register. One can find the circuit for bootstrap mode in appendix A of the PCBUG11 Manual or construct a circuit where MODA and MODB are tied to ground and IRQ, XIRQ, and RESET are pulled up through a 4.7K Ohm resistor. Transmit and Receive on the MCU must go through an RS232 Level shifter. The part number for socket E56, the Motorola level shifter, is MC145407. Please refer to the data sheet for more information. With PCBUG11 and Bootstrap mode on the 68HC11, getting to know the part is easy and inexpensive. 1999Mar04 68HC11 Misc., Memories How does the NOSEC bit work on the 68HC11 Family?
For the NOSEC bit to work on the 68HC11 Family of microcontrollers, the nomenclature on the micro must specify that the feature has been enabled. This option does not come enabled on all members of the family- 1999Mar04 68HC05, 68HC705V8, 68HC05V7 Serial Communication Can I run the 68HC705V8/68HC05V7 MDLC using nominal bit timing?
Symptom:
The MDLC module is capable of receiving messages successfully only when the bit timing is equal to or greater than the minimum values plus 5% of the nominal values, as published in the 68HC705V8 Specification Rev. 2.1. (Section 17.11.7)
Explanation:
Most customer run J1850 communications at nominal timing values and will never see this problem, however, it does exist (in the devices tested) and needs to be addressed.
Solution:
Simply increase the bit timing to above the threshold of minimum plus 5% nominal values. This should prevent any problems related to this bug. 1999Mar04
68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog What are the differences between the 68HC705JJ7/JP7 A/D conversion modes?
Mode 0
Mode 1
Mode 2
NOTE: Be sure to clear TOF before clearing ICF and always set the IEDG bit in TCR = 1
Mode 2 also allows for overtime testing using OCF to halt bad conversions sooner and make next TOF ready to start new conversions.
Mode 3
NOTE: Be sure to clear OCF before clearing ICF and always set the IEDG bit in TCR = 1.
Mode 3 cannot perform overtime test using OCF to halt bad conversions sooner. So a bad conversion will use the next OCF for a time limit, while the old conversion time is replaced.
Noise on the A/D system may adversely affect performance on A/D conversions. Following are some effects one can look for as well as possible solutions.
Effects
Possible solutions
Reference AN1740, Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog What are the differences between comparator 1 and comparator 2?
Comparator 1 and comparator 2 have many of the same characteristics. They both can compare voltages which are more than 1.5 volts below the VDD supply voltage. Input offset is typically 10 mV and typical response time is less than 1 second. Each comparator can have its internal circuitry flipped so that any input offset can be referenced to either input. They both can also be powered down to conserve supply current when its voltage comparison function is not needed. Both comparators have identical performance and differ only in how they are connected to external pins.
Comparator 1 is a basic voltage comparator with its positive and negative inputs tied permanently to the PB2 and PB3 pins, respectively. The output can be monitored by both dynamic output and static flag bits in the ASR (analog status register) located at address $001E. The dynamic output bit, CMP1, becomes a logical 1 whenever the comparator's positive input is above its negative input and it follows the output of the comparator regardless of its prior conditions. The static flag bit, CPF1, becomes set whenever there is a rising output from the comparator. CPF1 remains set until cleared by writing a logical1 to the reset bit, CPFR1. Comparator 1 also has the provision to connect its output to the PB4 pin by setting the COE1 bit in the ASR. This makes the comparator useful for directly driving some external function.
Comparator 2 is a basic voltage comparator with its positive input tied permanently to the PB0 pin and its negative input being tied to a number of internal or external functions. The negative input of comparator 2 can be switched to various sources, but in all cases the internal sample capacitor of approximately 10 pF will remain connected from the negative input to VSS or to a voltage offset of approximately 100 mV. Its output can be monitored by the dynamic output and static flag bits in the ASR located at address $001E. The dynamic output bit, CMP2, follows the output of the comparator regardless of its prior conditions. CMP2 becomes a logical 1 whenever the comparator's positive input is above its negative input. The static flag bit, CPF2, becomes set whenever there is a rising output from the comparator and remains set until cleared by writing a logical 1 to the reset bit, CPFR2. The primary purpose of comparator 2 is to construct a multiple channel integrating A/D converter using the internal channel MUX, internal references, input divider, and sample and hold.
Reference AN1740, Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog What is the general process for building an A/D converter with the 68HC705JJ7/JP7 Analog Subsytem?
The general process for building an A/D converter is:
Reference AN1740, Applications Using the Analog Subsystem of the MC68HC05JJ/JP Series Microcontrollers. 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog, General I/O Why should I disable pulldowns for analog signals into the comparators?
All I/O pins have internal pulldown devices which draw about 50-100 micro amps. These are primarily for the digital input pulldown of switches or other high-impedance lines. They can be a source of unwanted results if left active to analog signals. In particular, the pulldown device on PB0 can cause a rounded or RC like charge curve on the ramp capacitor when making a single slope A/D. Turn off the pulldowns to all analog signals by writing a 1 to the appropriate bits in the PDRA or PDRB.
Reference AN1740, Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers. 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog How does the 68HC705JJ7/JP7 comparator input impedance vary?
The analog inputs to the comparators (PB0:PB4) are very high impedance (about 1 M) when the pulldowns are off and the current source is not connected. The divider on the negative input to comparator 2 will reduce this input impedance to about 120K. In either case the input impedance of the negative input to comparator 2 will degrade with frequency due to the internal sample capacitor.
Reference AN1740, Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog How can I use the 68HC705JJ7/JP7 constant current source?
A constant current source and/or discharge device is connected to PB0 in order to construct single slope A/D. This current source and discharge device can be used for other purposes. The current source is only constant as long as the voltage on PB0 is within the common-mode range of VSS to VDD - 1.5 volts.
Reference AN1740, Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog What things should I consider when using the 68HC705JJ7/JP7 A/D Converter?
NOTE: Common Mode Range is defined by a fixed voltage drop below VDD. Typically VSS to VDD - 1.5 volts.
Reference AN1740, Applications Using the Analog Subsystem of the MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog Can the 68HC705JJ7/JP7 comparators be used in STOP mode?
The comparators can be active during STOP mode. They cannot, however, restart the device unless comparator 1 can drive an external RESET or IRQ pin. The comparators can latch in events that occurred during STOP mode and can direct external circuits (COE1 bit). There will be an increased draw on IDD (in the order of 165 mA for a single comparator).
Reference AN1740, Applications Using the Analog Subsystem of the MC68HC05JJ/JP Series Microcontrollers. 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog What are potential single-slope A/D fault conditions ?
Possible faults to consider when choosing single slope A/D are:
A/D fault conditions for all modes of operation
A/D fault conditions for mode 2 or mode 3
These faults are likely to be seen near the limits of its input voltage range, in the signal noise, and timing with respect to the software. All A/D conversion software should account for these possible faults to avoid unexpected results or lockup of the software.
Reference AN1740, Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Development Tools, Analog What should I consider when using an emulator with the 68HC705JJ7/JP7 analog subsystem?
Use of an emulator will introduce more system noise sources than will be seen in a typical single-chip application. The user should be aware of these limitations during development of software code. The emulator and its connected host PC can also induce unwanted signals onto low level or high impedance signal sources. Unexpected results should involve investigation of these effects before making changes to hardware and/or software.
Reference AN1741, In-Circuit Emulation Considerations for MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog, Misc. How should I use the sample capacitor in the JJ/JP analog subsystem?
The sample capacitor is connected between the negative input of the comparator and
either a 100mV offset or direct to VSS for the analog subsystem (AVSS). The sample capacitor is typically 10pF and charges very rapidly. It will usually reach 99.9% of its final value within 0.7 mSec when using the direct input and 6 mSec when using the divided input.
The sample capacitor can hold a charge for up to 4 - 5 minutes at room temperature. It is however, recommended that the following points be taken into consideration:
When sampling a signal remember to first turn off the holding MUX (HOLD or DHOLD) and change channels on a separate write cycle, and then connect the channel bus to the VREF internally.
Reference AN1740, Applications Using the Analog Subsystem of the MC68HC05JJ/JP Series Microcontrollers and AN1741, In-Circuit Emulation Considerations for MC68HC05JJ/JP Series Microcontrollers. 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 Analog, Misc. How can I use the 68HC705JJ7/JP7 temperature sensing diode?
The MCU contains an internal diode connected to VSS which will be sensitive to the temperature of the device. The tolerance on the 25C voltage and TC of this diode does not make it more accurate than about 10C, but it can be used as a first order temperature compensation for the device. The user will require calibration of the diode for more precise temperature measurements. This calibration data may be stored in the Personality EPROM found on some JJ/JP Family members.
Reference AN1740, Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC05, 68HC705JP7, 68HC05JP6, 68HC705JJ7, 68HC05JJ6 EMI, EMC, ESD, Misc. What should I consider when laying out a 68HC705JJ7/JP7 board?
Reference AN1741, In-Circuit Emulation Considerations for MC68HC05JJ/JP Series Microcontrollers . 12-Jul-99 68HC11 Misc. Describe the enhancements on the M68HC11 Bootstrap Mode.
Refer to engineering bulletin EB422/D. 1999Jul22 68HC11KS2, 68HC11KA4, 68HC11KA2 Misc. What features on the 68HC11KA4, KA2 MCUs were changed when going to the 68HC11KS2/KS8 MCUs?
Refer to engineering bulletin EB312/D. 1999Jul22 68HC11 Memories, Misc. How do I eliminate intermittent programming and execution failures with 68HC11 windowed EPROM MCUs?
Refer to engineering bulletin EB303/D. 1999Jul22 68HC811E2, 68HC11 Memories, Development Tools How you program the EEPROM on the MC68HC811E2 during program execution?
Refer to engineering bulletin EB301/D. 1999Jul22 68HC711D3, 68HC11 Misc. Why the M68HC711D3PGMR software does not run on 486 33-MHz computers.
Refer to engineering bulletin EB299/D. 1999Jul22 68HC711E9, 68HC11 Memories, Development Tools How do I program the BUFFALO monitor into a 68HC711E9?
Refer to engineering bulletin EB298/D. 1999Jul22 68HC711E9, 68HC11 Memories, Development Tools How do I program the 68HC711E9 using PCbug11 and the 68HC11EVBU?
Refer to engineering bulletin EB296/D. 1999Jul22 68HC811E2, 68HC11 Memories, Development Tools How do I program the EEPROM of the 68HC811E2 using the M68HC11EVM?
Refer to engineering bulletin EB295/D. 1999Jul22 68HC11 CPU, Instructions, Misc. How do I write to the 64-cycle time-protected registers on 68HC11 MCUs?
Refer to engineering bulletin EB294/D. 1999Jul22 68HC711E20, 68HC11 Memories, Development Tools How do I program the 68HC711E20 using theM68HC711E9 PGMR?
Refer to engineering bulletin EB293/D. 1999Jul22 68HC11 Development Tools, Misc. What do I need to consider when moving from the BUFFALO monitor to a stand alone 68HC11?
Refer to engineering bulletin EB292/D. 1999Jul22 68HC811E2, 68HC11 Memories, Development Tools How do I program the 68HC811E2 using the PC bug11 and the M6868HC11EVBU?
Refer to engineering bulletin EB291/D. 1999Jul22 68HC11F1 Development Tools Describe the 68HC11F1 C macro definitions.
Refer to engineering bulletin EB289/D. 1999Jul22 68HC11E9, 68HC711E9, 68HC11E1, 68HC11E0 Development Tools Describe the 68HC11 E Family C macro definitions?
Refer to engineering bulletin EB287/D. 1999Jul22 68HC711E20, 68HC11E20 Development Tools Describe the 68HC(7)11E20 C macro definitions.
Refer to engineering bulletin EB285/D. 1999Jul22 68HC711D3, 68HC11D3, 68HC11D0 Development Tools Describe the 68HC11 D Family C macro definitions?
Refer to engineering bulletin EB284/D. 1999Jul22 68300, 68F333 Memories, Electrical Specification Why must I never reduce the programming voltage pin below VDD on 68F333s?
Refer to engineering bulletin EB254/D. 1999Jul22 68HC11 EMI, EMC, ESD How do I reduce emitted noise on 68HC11's?
Refer to engineering bulletin EB198/D. 1999Jul22 68HC11 Exceptions, Interrupts, Development Tools How do I use pseudo-interrupt vectors on the M68HC11EVBU?
Refer to engineering bulletin EB197/D. 1999Jul22 68HC11 Exceptions, Interrupts How do I configure the RESET pin on 68HC11's?
Refer to engineering bulletin EB195/D. 1999Jul22 68HC11E9, 68HC11E1, 68HC11E0, 68HC11A8, 68HC11A1, 68HC11A0 Misc. How do I migrate from the 68HC11 A Family to the 68HC11 E Family?
Refer to engineering bulletin EB193/D. 1999Jul22 68HC11K, 68HC11KA, 68HC11KW, 68HC11P, 68HC11PH, 68HC711K, 68HC711P, 68HC711PH, 68HC711KW Timer Provide a PWM tutorial for 68HC11 K, KA, KW, P, and PH families.
Refer to engineering bulletin EB192/D. 1999Jul22 68HC711E9, 68HC811E2, 68HC11E1, 68HC11E0 Memories, Development Tools How do I program EEPROM and EPROM 68HC11 E Family MCUs using the M68HC11EVM?
Refer to engineering bulletin EB191/D. 1999Jul22 68HC811E2, 68HC11 Memories, Development Tools How do I program the 68HC811E2 using the M68HC711E9 PGMR?
Refer to engineering bulletin EB189/D. 1999Jul22 68HC811E2, 68HC11 Memories, Development Tools How do I enable security on the 68HC811E2 using the M68HC711E9 PGMR?
Refer to engineering bulletin EB188/D. 1999Jul22 68HC711E9, 68HC11 Memories, Development Tools How do I program the 68HC711E9 using the M68HC11EVB?
Refer to engineering bulletin EB187/D. 1999Jul22 68HC711E9, 68HC11 Memories, Development Tools How do I program the 68HC711E9 using the M68HC711E9 PGMR?
Refer to engineering bulletin EB185/D. 1999Jul22 68HC711E9, 68HC11 Memories, Development Tools How do I enable security on the 68HC711E9 using the M68HC711E9 PGMR?
Refer to engineering bulletin EB184/D. 1999Jul22 68HC11E9, 68HC11E0, 68HC11E1 Memories, Misc. How does the ROMON bit behave on the 68HC11 E Family?
Refer to engineering bulletin EB182/D. 1999Jul22 68HC11E32, 68HC11PH8 Development Tools Describe using the ROMed 68HC11E32 and 68HC11PH8 with BUFFALO monitor and PCvug11 Talker?
Refer to engineering bulletin EB419/D. 1999Jul22 68HC11ED0 Development Tools Describe the 68HC11ED0 C macro definitions.
Refer to engineering bulletin EB288/D. 1999Jul22 68HC11A8, 68HC11A1, 68HC11A0 Development Tools Describe the 68HC11A Family C macro definitions.
Refer to engineering bulletin EB286/D. 1999Jul22 68HC11C0 Development Tools Describe the 68HC11C0 C macro definitions.
Refer to engineering bulletin EB283/D. 1999Jul22 68HC12, 68HC912B32 Memories, Development Tools How do I erase and program the FLASH EEPROM on the 68HC912B32?
Refer to engineering bulletin EB183/D. 1999Jul22 68HC16 Development Tools Why am I having problems with exercise 8 of the 68HC16EVB?
Refer to engineering bulletin EB309/D. 1999Jul22 68HC16 Development Tools Why am I having word alignment problems on exercise 7 of the M68HC16EVB?
Refer to engineering bulletin EB306/D. 1999Jul22 68HC16, 68300, Development Tools, Memories How do I eliminate startup problems when booting from RAM using a background Debug Monitor (BDM)?
Refer to engineering bulletin EB305/D. 1999Jul22 68HC16, 68300, MPC500 Timer How do I use the output compare function of the Time Processor Unit (TPU)?
Refer to engineering bulletin EB282/D. 1999Jul22 68HC16, 68300, Serial Communication How do I stop and start the Queued Serial Peripheral Interface on 68HC16 and 68300 MCUs?
Refer to engineering bulletin EB281/D. 1999Jul22 68HC16, 68300, Timer How do I program the channel control registers on the time Processor Unit (TPU)?
Refer to engineering bulletin EB280/D. 1999Jul22 68HC16, 68300, Bus Interface, General I/O When would I see low output levels on 68300 and 68HC16 MCUs?
Refer to engineering bulletin EB279/D. 1999Jul22 68HC16, 68300, MPC500, MCORE Timer What is the latency when using the Time processing Unit (TPU)?
Refer to engineering bulletin EB278/D. 1999Jul22 68HC16, 68300, MPC500, MCORE Misc. What is the coherency in the Time Processor Unit (TPU)?
Refer to engineering bulletin EB277/D. 1999Jul22 68HC16, 68300, MPC500 Timer How do I use the ITC function on the Time Processor Unit (TPU) ?
Refer to engineering bulletin EB276/D. 1999Jul22 68HC16, 68300, Serial Communication How do I use the Queued Serial Peripheral Interface (QSPI) on 68HC16 and 68300 MCUs?
Refer to engineering bulletin EB275/D. 1999Jul22 68HC16, 68300, MPC500 Timer, Exceptions, Interrupts How do I generate interrupts on the Time Processor Unit (TPU)?
Refer to engineering bulletin EB274/D. 1999Jul22 68332, 68331, 68300, 68HC16Z1 Bus Interface, General I/O Which pins of 68331/68332 and 68HC16Z1 need pull up resistor?
Refer to engineering bulletin EB273/D. 1999Jul22 68332, 68300 Timer Why am I having trouble using the 24-bit mode of the PPWA function on revision P of 68332 MCUs?
Refer to engineering bulletin EB270/D. 1999Jul22 68HC16, 68300 Serial Communication How do I use the 68HC16 and 68300 SCI?
Refer to engineering bulletin EB269/D. 1999Jul22 68HC16, 68300 Timer, Development Tools How do I start and stop the Time processor Unit (TPU) clock using the background delay module (BDM)?
Refer to engineering bulletin EB268/D. 1999Jul22 68300 Bus Interface, Exceptions, Interrupts What is a double bus fault monitor?
Refer to engineering bulletin EB267/D. 1999Jul22 68HC16, 68300 Bus Interface, Exceptions, Interrupts Why could I see unexplained three-stating of the address bus on 68300 and 68HC16 devices?
Refer to engineering bulletin EB266/D. 1999Jul22 68HC16, 68300 Exceptions, Interrupts How do I generate edge sensitive interrupts on 68300 and 68HC16 MCUs?
Refer to engineering bulletin EB265/D. 1999Jul22 68HC16, 68300 Exceptions, Interrupts How do I disable all interrupts on Power-On for 68300 and 68HC16 MCUs?
Refer to engineering bulletin EB264/D. 1999Jul22 68HC16, 68300 Bus Interface, General I/O How do I program chip selects on 68HC16 and 68300 MCUs?
Refer to engineering bulletin EB263/D. 1999Jul22 68HC16, 68300 Bus Interface, General I/O What happens if a chip select is programmed as either a discrete output or alternate function in the chip assignment register (CSPARX), but the chip-select base address (CSBARX) and chip-select option r
Refer to engineering bulletin EB262/D.
Refer to engineering bulletin EB262/D. 1999Jul22 68HC16, 68300 Bus Interface, Exceptions, Interrupts How do I generate autovectors using chip select logic on 68300 and 68HC16 MCUs?
Refer to engineering bulletin EB261/D. 1999Jul22 68HC16, 68300 Exceptions, Interrupts Why 68300 and 68HC16 MCUs may fail to release reset?
Refer to engineering bulletin EB260/D. 1999Jul22 68HC16, 68300 Exceptions, Interrupts Why 68300 and 68HC16 MCUs may halt after the release of the reset?
Refer to engineering bulletin EB259/D. 1999Jul22 68HC16, 68300 Exceptions, Interrupts What are the RESET sources on 68HC16 and 68300 MCUs?
Refer to engineering bulletin EB258/D. 1999Jul22 68HC16, 68300 Clocking How do I detect the loss of clock on 68HC16 and 68300 MCUs?
Refer to engineering bulletin EB257/D. 1999Jul22 68HC16, 68300 Memories How do I use the Lock bit on FLASH 68300 and 68HC16 MCUs?
Refer to engineering bulletin EB256/D. 1999Jul22 68300 CPU, Instructions How do I use the 68300 table lookup and interpolate instruction?
Refer to engineering bulletin EB253/D. 1999Jul22 68HC16 Development Tools What are the MOVB, MOVW, PSHM, PULM syntax differences on 68HC16 assembler?
Refer to engineering bulletin EB252/D. 1999Jul22 68HC16 CPU, Instructions How do I calculate instruction times on the 68HC16?
Refer to engineering bulletin EB251/D. 1999Jul22 68300 Exceptions, Interrupts How do I diagnose CPU32 released write faults using bus error stack frames?
Refer to engineering bulletin EB310/D. 12-Jul-99 68HC16, 68300 Misc. What are common startup problems when using a software background mode debugger and booting from RAM or an empty ROM socket?
Refer to engineering bulletin EB305/D. 12-Jul-99 68HC05, 68HC05BD3 Misc. How can I emulate the DDC1 hardware in software using the 68HC05BD3?
Refer to application note AN-HK-24/H. 1999Jul22 6805R3, 68HC705SR3, 68HC05SR3 Misc. How can I migrate from the 6805R3 to the 68HC05SR3?
Refer to application note AN-HK-23/H. 1999Jul22 68HC705SR3, 68HC05SR3 Misc. What known issues exist regarding the 68HC705SR3, and how do I convert to it from the 68705R3?
The 68HC705SR3 is intended to be a replacement for the NMOS 68705R3/U3. There are some considerations however, when using the 68HC705SR3. These are documented in application note AN-HK-23/H, MC6805R3 and MC68HC05SR3 Technical Comparison and application note AN-HK-22/H, MC68HC05SR3 and MC68HC705SR3 Design Notes.
* If you want to use code from the R3 to the SR3, make sure you adjust all memory locations to reflect the memory map of the SR3. Ensure all options that are selected through mask option registers or option registers match in the two devices.
* The VPP pin on the SR3 should be tied to the VDD supply voltage for normal operation. This pin supplies VPP supply for programming, but during user-mode operation it should be tied to VDD. Do not leave this pin floating, and do not connect it to VSS.
* When using the A/D Converter on the 68HC705SR3, all other Port D pins will not be accessible as digital pins. This includes the digital only PD7. While the ADON bit is set, all Port D pins are reserved, and cannot be digitally read or written. This is a known issue with the 68HC705SR3. 1999Jul22 68HC05F2 Analog, Misc. How can I implement a low-cost, low-voltage active filter for 68HC05F2 DTMF output?
Refer to application note AN-HK-17/H. 1999Jul22 68HC05F6 Misc. How can I use the 68HC05F6 as a tone pulse dialer with melody on-hold?
Refer to application note AN-HK-12/H. 1999Jul22 68HC05 Serial Communication, Timer How can I use the 68HC05 16-bit timer for an interrupt driven SCI?
Refer to application note AN4002/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12 Clocking How can I determine MCU oscillator start-up parameters?
Refer to application note AN1783/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE Analog, General I/O How can I expand digital inputs with an A/D converter?
Refer to application note AN1775/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12 CPU, Instructions, Misc. How can I implement precision sine wave tone synthesis using Motorola 8-bit MCUs?
Refer to application note AN1771/D. 1999Jul22 68HC705L16, 68HC05 Misc. How can I drive LCD displays using the 68HC705L16?
Refer to application note AN1763/D. 1999Jul22 68HC705C8A, 68HC05 Memories, Serial Communications, Misc. How can I interface the X76F041 PASS secure Flash to Motorola MCU's?
Refer to application note AN1761/D. 1999Jul22 68HC05, 68HC08 Serial Communication, Misc. How can I interface the AD8402 digital potentiometer to Motorola MCU's?
Refer to application note AN1760/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC05 Serial Communication, Misc. How can I add a non-volatile clock to Motorola MCUs?
Refer to application note AN1759/D. 1999Jul22 68HC05 Serial Communication, Misc. How can I add addressable switches to the 68HC05 Family?
Refer to application note AN1758/D. 1999Jul22 68HC05, 68HC08 Memories, Serial Communication How can I interface the DS2430A 256-bit 1-wire EEPROM to Motorola MCUs?
Refer to application note AN1755/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC05 Serial Communication, General I/O, Misc. How can I interface the DS1620 digital thermometer to Motorola MCUs?
Refer to application note AN1754/D. 1999Jul22 68HC05, 68HC08 CPU, Instructions, Misc. How can I implement data structures in Motorola 8-bit MCUs?
Refer to application note AN1752/D. 1999Jul22 68HC805K3, 68HC705K1, 68HC05 Misc. How can I migrate from the 68HC705K1 to the 68HC805K3?
Refer to application note AN1747/D. 1999Jul22 68HC705KJ1, 68HC705K1, 68HC05 Misc. How can I migrate from the 68HC705K1 to the 68HC705KJ1?
Refer to application note AN1746/D. 1999Jul22 68HC705C8A, 68HC05, 68HC08 Serial Communication, Misc. How can I interface LCD modules to Motorola MCUs?
Refer to application note AN1745/D. 1999Jul22 68HC05, 68HC08, 68HC11 Exceptions How do I handle resetting MCUs during power transitions?
Refer to application note AN1744/D. 1999Jul22 68HC705L16, 68HC05 CPU, Instructions, Misc. How can I write scrolling message software for LCD MCUs?
Refer to application note AN1743/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC05 Memories How can I program the 68HC705J1A in-circuit?
Refer to application note AN1742/D. 1999Jul22 68HC705JP7, 68HC705JJ7, 68HC05JJ6, 68HC05JP6 Development Tools What should I consider when emulating the 68HC(7)05JJ/JP MCUs?
Refer to application note AN1741/D. 1999Jul22 68HC705JP7, 68HC705JJ7, 68HC05JJ6, 68HC05JP6 Analog How can I use the analog subsystem of the 68HC(7)05JJ/JP MCUs?
Refer to application note AN1740/D. 1999Jul22 68HC705JP7, 68HC705JJ7, 68HC05JJ6, 68HC05JP6 CPU, Instructions, Misc. How can I measure instruction timing on 68HC05 MCUs?
Refer to application note AN1738/D. 1999Jul22 68HC705J2, 68HC705JJ7, 68HC05 Misc. How can I migrate from the 68HC705J2 to the 68HC705JJ7?
Refer to application note AN1737/D. 1999Jul22 68HC705P9, 68HC705P6A, 68HC05P1A, 68HC05P4A, 68HC05P7A, 68HC05P9A, 68HC05P8 Misc. Describe the variations in the 68HC05 P Family.
Refer to application note AN1736/D. 1999Jul22 68HC705C8A, 68HC05 Timer How can I implement PWMs using the 68HC05s 16-bit capture/compare timers?
Refer to application note AN1734/D. 1999Jul22 68HC705P9, 68HC705P6A, 68HC05 Misc. How can I implement caller ID functionality using Motorola MCUs?
Refer to application note AN1733/D. 1999Jul22 68HC05, 68HC705J1A, 68HC705KJ1 Analog, Misc. How can I implement digital amplification control of an analog signal using Motorola MCUs?
Refer to application note AN1730/D. 1999Jul22 68HC05, 68HC08 General I/O, Misc. How can I interface IBM AT keyboards to 68HC05 MCUs?
Refer to application note AN1723/D. 1999Jul22 68HC705C9A, 68HC705C8A, 68HC05C4A, 68HC05C8A, 68HC05C9A Misc. Describe the variations in the 68HC05 C Family
Refer to application note AN1298/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC05 Misc. How can I add voice add a voice user interface to 68HC05 applications?
Refer to application note AN1292/D. 1999Jul22 68HC805K3, 68HC05K3 Memories, Development Tools How can I program the 68HC(8)05K3's personality EEPROM (PEEP) using the MMDS or MMEVS development systems?
Refer to application note AN1288/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE EMC, EMI, ESD How can I design for electromagnetic compatibility with single-chip MCUs?
Refer to application note AN1263/D. 1999Jul22 68HC05, 68HC08 CPU, Instructions, Development Tools, Misc. How can I implement a simple real-time kernal in 68HC05 MCUs?
Refer to application note AN1262/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE EMC, EMI, ESD What system design and lay out techniques should I use for noise reduction in MCU based system?
Refer to application note AN1259/D. 1999Jul22 68HC705V8, 68HC05V7 Analog How can I use the 68HC05 Family On-Chip voltage regulator?
Refer to application note AN1257/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC705C8A, 68HC05 Analog, Serial Communication How can I interface serial Multi-channel digital-to analog converters to Motorola MCUs?
Refer to application note AN1256/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC05 Memories, Serial Communications How can I interface a 356/9366 serial EEPROMs to Motorola MCUs?
Refer to application note AN1241/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC05 CPU, Instructions, Serial Communication How can I communicate serially using MCUs without a hardware UART/SCI?
Refer to application note AN1240/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC05 General I/O How can I decode keypad inputs using Motorola MCUs?
Refer to application note AN1239/D. 1999Jul22 68HC705J1A, 68HC705KJ1, 68HC05 General I/O How can I interface LEDs to Motorola MCUs?
Refer to application note AN1238/D. 1999Jul22 68HC705C8A, 68HC705C9A, 68HC05 Analog, Serial Communication How can I interface the MC140551 A/D convertor with Motorola MCUs?
Refer to application note AN1228/D. 1999Jul22 68HC705C8A, 68HC705C9A, 68HC05 Memories, Serial Communications How can I interface 9346 series serial EEPROMs with Motorola MCUs?
Refer to application note AN1227/D. 1999Jul22 68HC705C8A, 68HC705C9A, 68HC05 Misc. How can I migrate from the 68HC705C8 to the 68HC705C8A?
Refer to application note AN1226/D. 1999Jul22 68HC705V8, 68HC05V7 J1850 Provide example software routines for the message data link controller module on the 68HC705V8?
Refer to application note AN1224/D. 1999Jul22 68HC05, 68HC08 CPU, Instructions, Misc. How can I implement arithmetic waveform synthesis with 68HC05 and 68HC08 MCUs?
Refer to application note AN1222/D. 1999Jul22 68HC05, 68HC08 CPU, Instructions How can I optimize 68HC05 code to run most efficiently on 68HC08 MCUs?
Refer to application note AN1218/D. 1999Jul22 SC371016, 68HC705C8A J1850 How can I use the SC371016 J180 Communications Interface (JCI) with a 68HC05 MCU?
Refer to application note AN1212/D. 1999Jul22 68HC705B16, 68HC705B32, 68HC05 Analog, Timer, Misc. How do I implement a basic servo loop motor control using the 68HC05 B Family?
Refer to application note AN1120/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE Timer How can I generate and detect pulses using Motorola MCUs?
Refer to application note AN1067/D. 1999Jul22 68HC05C5 Serial Communication How can I interface the 68HC05C5 SIOP to an I2C peripheral?
Refer to application note AN1066/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE Misc. How do I select the best MCU from Motorola's broad offering?
Refer to application note AN1057/D.
This application note refers to an old selector guide. Use our web selector guide instead. 1999Jul22 68HC05 CPU, Instructions Describe the 6805 16-bit support macros?
Refer to application note AN1055/D. 1999Jul22 68HC05 EMC, EMI, ESD How can I design for electromagnetic compatibility (EMC) with MCUs?
Refer to application note AN1050/D. 1999Jul22 68HC05, 68HC08 Serial Communication How can I use the serial peripheral interface (SPI) to communicate between multiple MCUs?
Refer to application note AN991/D. 1999Jul22 68HC705, 68HC05 Memories, Development Tools How can 68HC705 MCUs program themselves?
Refer to application note AN499/D. 1999Jul22 68HC05, 68HC08 Analog How can I get a low-cost A/D capability in MCUs without an integrated A/D?
Refer to application note AN477/D. 1999Jul22 68HC05 Controller Area Network (CAN) How do I write driver routines for the 68HC05 CAN Module?
Refer to application note AN464/D. 1999Jul22 68HC05K0 Misc. How do I do infra-red remote control using 68HC05s?
Refer to application note AN463/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE Misc. How can I drive LCDs using a MCU without integrated LCD drivers?
Refer to application note AN442/D. 1999Jul22 68HC705B16, 68HC705B32, 68HC05 Memories How do I program the 68HC05 B Family EEPROM using a serial bootloader out of RAM?
Refer to application note AN434/D. 1999Jul22 68HC705B16, 68HC705B32, 68HC05 CPU, Instructions, Analog, Misc. How do I do temperature measurement and display using 68HC05 B Family MCUs?
Refer to application note AN431/D. 1999Jul22 68HC705B16, 68HC705B32, 68HC05 CPU, Instructions, Serial Communication, Misc. Describe a simple monitor for 68HC05 B MCU's
Refer to application note AN420/D. Note: This application note refers to a mask ROM XC68HC05B6FN monitor that is no longer available. 1999Jul22 68HC08, 68HC708MP16, 68HC908MR24, 68HC08 Misc. How can I migrate 68HC708MP16 applications to the 68HC908MR24?
Refer to application note AN1792/D. 1999Jul22 68HC05, 68HC08, 68HC11 CPU, Instructions, Misc. How can I implement precision sine-wave tone synthesis using 8-bit MCUs?
Refer to application note AN1771/D. 1999Jul22 68HC908GP20, 68HC08 Memories, Development Tools How can I In-circuit program the 68HC908GP20?
Refer to application note AN1770/D. 1999Jul22 68HC708KH12, 68HC08KH12 Serial Communication, Universal Serial Bus, Misc. How can I build a Universal Serial Bus (USB) keyboard hub using the 68HC(7)08KH12?
Refer to application note AN1748/D. Note: the 68HC908KH12 should read 68HC708KH12. 1999Jul22 68HC908MR24, 68HC708MP16 Timer, Motor Control, Misc. How can I implement motor control using the 68HC708MP16 and 68HC908MR24?
Refer to application note AN1712/D.
Note: The 68HC708MP16 is being replaced with the 68HC908MR24. Refer to AN1792, using the 68HC908MR24 in place of the 68HC708MP16. 1999Jul22 68HC08 CPU, Instructions How can I make integer math routines for the 68HC08?
Refer to application note AN1219/D. 1999Jul22 68HC912B32, 68HC12 Misc. How can I interface the 68HC912B32 to an LCD module?
Refer to application note AN1744/D. 1999Jul22 68HC711E9, 68HC11 Memories, Bus Interface How can I implement a FLASH memory system in a 68HC711E9 design?
Refer to application note AN1753/D. 1999Jul22 68HC11E9, 68HC711E9 Analog, Timer, Motor Control, Misc. How can I implement stepper motor control with 68HC11 MCUs?
Refer to application note AN1285/D. 1999Jul22 68HC11, 68HC12 CPU, Instructions, Misc. How can I migrate 68HC11 code to the 68HC12?
Refer to application note AN1284/D. 1999Jul22 68HC11, 68HC16 CPU, Instructions, Misc. How can I migrate 68HC11 code to the 68HC16?
Refer to application note AN1283/D. 1999Jul22 68HC11K4, 68HC11N4 CPU, Instructions, Analog, Timer, Misc. How can I implement PID (proportional, integral, derivative) routines for the 68HC11K4 and 68HC11N4 MCUs?
Refer to application note AN1215/D. 1999Jul22 68HC11 CPU, Instructions How can I use the 68HC11's stack to simplify programming?
Refer to application note AN1064/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE Analog How can I reduce A/D errors in MCU applications?
Refer to application note AN1058/D. 1999Jul22 68HC11 Memories How can I program 68HC11 EEPROM using a personal computer?
Refer to application note AN1010/D. 1999Jul22 68HC11 Misc. What are 68HC11 CONFIG register issues?
Refer to application note AN997/D. 1999Jul22 68HC11 Serial Communication, Misc. How can I use the 68HC11 bootstrap mode?
Refer to application note AN1060/D. 1999Jul22 68HC11 CPU, Instructions How can I implement floating-point routines for the 68HC11?
Refer to application note AN974/D. 1999Jul22 68HC11 Misc. How can I implement a 68HC11 controlled multiband RDS radio?
Refer to application note AN494/D. and application note AN495/D. 1999Jul22 68HC11, 68HC16 CPU, Instructions, Misc. What are the differences between the 68HC16 and 68HC11?
Refer to application note AN461/D. 1999Jul22 68HC11 CPU, Instructions, Memories How can I implement 68HC11 EEPROM error correction algorithms in C?
Refer to application note AN427/D. 1999Jul22 68HC11 Misc. How can I use the 68HC11 to implement an IEEE-488 interface to the DSP56000?
Refer to application note AN415/D. 1999Jul22 68HC912B32, 68HC12 Misc. How can I interface the 68HC912B32 to an LCD module?
Refer to application note AN1774/D. 1999Jul22 68HC912B32, 68HC12 Memories, Serial Communications How can I implement a serial bootloader for reprogramming the 68HC912B32 FLASH EEPROM?
Refer to application note AN1718/D. 1999Jul22 68HC12 CPU, Instructions How can I use 68HC12 indexed indirect addressing?
Refer to application note AN1716/D. 1999Jul22 68HC12 CPU, Instructions, Misc. How can I demonstrate fuzzy TECH for the 68HC12?
Refer to application note AN1295/D. 1999Jul22 MPC505, MPC509, MPC500 Misc. What can I ensure optimum frequency synthesizer performance using the MPC505 and MPC509 PLL?
Refer to application note AN1282/D. 1999Jul22 68HC16Z1 CPU, Instructions, Misc. How can I use the 68HC16Z1 for audio tone generation?
Refer to application note AN1254/D. 1999Jul22 68HC16Z1 Timer, Misc. How can I implement brushed DC motor control using the 68HC16Z1?
Refer to application note AN1249/D. 1999Jul22 68300 Serial Communication How can I implement SCI receive and transmit buffers in C?
Refer to application note AN1724/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE EMI, EMC, ESD What are noise reduction techniques for MCU based systems?
Refer to application note AN1705/D. 1999Jul22 68HC11 Misc. How can I implement longwave radio data decoding using the 68HC11 and the MC3371?
Refer to application note AN1597/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MPC500, MCORE Clocking What are MCU oscillator circuit design considerations?
Refer to application note AN1706/D. 1999Jul22 68HC11, 68HC12 CPU, Instructions How can I perform optical character recognition using fuzzy logic?
Refer to application note AN1220/D. 1999Jul22 68HC08 CPU, Instructions, Misc. What are hamming error control coding techniques with the 68HC08 MCU?
Refer to application note AN1221/D. 1999Jul22 68HC11 Memories, Bus Interface How can I use 68HC11 MCUs with WSI programmable peripheral devices?
Refer to application note AN1237/D. 1999Jul22 68HC908MR24, 68HC708MP16, 68HC08 Timer, Motor Control, Misc. How can I implement low-distortion motor waveforms using the 68HC708M16 and 68HC908MR24?
Refer to application note AN1728/D. Note: The 68HC708MP16 is being replaced with the 68HC908MR24. Refer to AN1792, using the 68HC908MR24 in place of the 68HC708MP16. 1999Jul22 68HC16 Timer How can I use the configurable timers module (CTM) in engine control?
Refer to application note AN476/D. 1999Jul22 68HC16, 68300 Timer What are the timing relationships between the Time Processor Unit (TPU) I/O Pins and the system clock used to drive the TPU module?
Refer to application note AN1236/D. 1999Jul22 68HC16 CPU, Instructions, Misc. How can I build an audio frequency analyzer with the 68HC16's digital signal processing (DSP)?
Refer to application note AN1233/D. 1999Jul22 68HC16, 68300 Development Tools How can I enable and control the Background Debug Module (BDM) using a personal computer?
Refer to application note AN1230/D. 1999Jul22 68HC16Z1 Misc. How can I implement DSP servo control with the 68HC16Z1?
Refer to application note AN1213/D. 1999Jul22 68HC16, 68300 Analog, Serial Communication How can I use the Queued Serial Peripheral Interface (QSPI) for analog data acquisition?
Refer to application note AN1062/D. 1999Jul22 MPC555, MPC500 Timer, General I/O How can I use the MPC555 MIOS?
Refer to application note AN1778/D. 1999Jul22 MPC505, MPC500 Exceptions How does the MPC505 interrupt controller work?
Refer to application note AN1281/D. 1999Jul22 68376, 68300 Controller Area Network (CAN), Misc. How can I implement stereo audio transmission over the CAN bus using the 68376 TOUCAN module?
Refer to application note AN1776/D. 1999Jul22 68332, 68300 Misc., Motor Control How can I use the 68332 for AC induction motor control?
Refer to application note AN1310/D. 1999Jul22 68HC16, 68300 Timer How do I configure Time Processor Unit (TPU)?
Refer to application note AN1200/D. 1999Jul22 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300 Clocking How do I determine the Crystal Drive Level?
Crystal drive level is the power it takes to drive the crystal. It is important in that it directly relates to power dissipation of a crystal (refer to faq on how to reduce crystal power dissipation).
For a Pierce Circuit and a circuit with a load capacitance in series with a crystal, the following equation may be used.
P = 2 x R1 x [PI x F x (CL+CO) x V]
Where:
CL = Load capacitance1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300 Clocking How Can I Reduce Crystal Power Dissipation?
CO = Shunt capacitance (and the sum of the electrode capacitance of the crystal and package capacitance)
F = Frequency
IC = RMS current through the crystal
P = Power
PI = 3.14...
R1 = Crystal resistance
V = VOLtage across the crystal
Crystal power dissipation can cause unstable operation by overdriving the crystal. If not accounted for it may even cause the quartz to actually break in extreme cases. Listed below are some steps that may be used to limit crystal power dissipation.
There are three questions one should consider when discussing series vs parallel crystal oscillator circuits.
In parallel circuits, such as the pierce, the crystal resonates with external capacitors and thus the crystal operates between the lowest impedance frequency and highest impedance frequency, where the impedance is inductive. This means that the operating frequency will be just above the lowest impedance frequency. When the load capacitor is placed in series with the resonator, the low impedance frequency is shifted up. Effective resistance at the new resonance frequency is higher than that of the resonator alone. This resistance is referred to as ESR. When the load capacitor is placed in parallel with the resonator, the anti-resonant frequency is shifted down. The resistance at this frequency is referred to as EPR. Note that ESR and EPR are equal.
Series load capacitance is used to measure the resonator's operating frequency. This is because the lower impedance is easier to measure. Parallel load capacitance, however, is most frequently used. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300 Clocking How do I determine the series resistance Rs for an oscillator circuit?
Rs is the series resistor in a basic oscillator circuit. Combined with a capacitor (C1 or C2 in pi circuit), it provides a phase shift. Rs also limits the power into the Crystal. Rs is generally used in low frequency designs.
Note: A range for Rs is usually provided by the crystal manufacturer.
Use the following steps to help determine Rs:
Rs must be large enough to limit current to the crystal, yet small enough to provide enough current to start oscillation quickly. Varying the size of Rs can vary the startup time for the oscillator. The smaller Rs is the faster the oscillator will startup. Choosing a to small Rs could cause startup to occur in unpredictable modes or to dissipate too much power. An Rs value that is too large could cause the oscillator to fail to start at all. Refer to the faq on how to determine Rs.
Refer to 68331/332TUT/D: An Introduction to the MC68331 and MC68332. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300 Clocking How does grit and grime affect oscillator performance?
Oscillators are very sensitive to dirt, moisture, and any other conductive substance on the PC board. These materials can cause high resistance leakage path from one of the amplifier pins to either ground or the positive terminal of the power supply. Low frequency crystal circuits tend to have a very high impedance. It is best to eliminate contaminants on the PC board. The feedback resistor (RF) can be reduced so that the impedance is not as significant.
Refer to 68331/332TUT/D: An Introduction to the MC68331 and MC68332. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE, MPC500 Clocking What do I need to consider when doing lay out with an oscillator?
A canned resonator is a single package that includes the oscillator and all required external components. The canned resonator can be used to help provide noise immunity. The package for a canned resonator is electrically shielded. Its rise and fall time is much faster than a crystals. With less transition time, there is a smaller chance of pulses occurring. 1999Mar04 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300 Clocking, EMC What things should I consider when designing for EMC without a canned oscillator?
Always note that a canned oscillator is always best when dealing with EMC issues. In the event that a canned oscillator is not an option the following should help to reduce the amount of noise emulating from the circuit.
Buffered inverters should not be used for crystal oscillator designs. They usually have a gain greater than 100. With a higher gain, one might see a spur, harmonic, or overtone caused by the part running at the wrong frequency or between frequencies. Buffered gates, however, can offer some advantages. High gain will result in a very fast internal transition time, causing a reduction in the amount of operating current. 1999Mar04 68HC05 Clocking How do I use an external clock with 68HC05s?
Some applications have a suitable clock provided that could be used in place of an external crystal or ceramic resonator. Using an external clock into the OSC1 (input) pin of the oscillator may not be sufficient to drive the MCU. The gain of the internal oscillator inverter of most new 68HC05s is very low (a gain of 3 to 5 is common) as this prevents the crystal from being overdriven and creating excessive EMI.
It is recommended that the oscillator be driven with an additional inverted signal into OSC2. This simulates the action of the crystal and drives the oscillator properly. An advantage of this is often improved EMS performance (immunity to noise) where the clock has fast edges and does not allow injection of noise spikes into the oscillator circuit of the MCU.
1999Mar04 68HC05, 68HC705X32, 68HC08, 68HC908AZ60, 68HC12, 68HC912BC32, 68HC16, 68300 Controller Area Network (CAN) What are CAN bit timing requirements?
Refer to application note AN1798/D. 1999Oct13 68HC08, 68HC908GP32 Memories, Development Tools How do I in-system program the 68HC908GP32?
Refer to application note AN-HK-32/H. 1999Oct13 68HC08, 68HC908JL3, 68HC908JK3, 68HC908JK1 Memories, Development Tools How do I in-system program the 68HC908JL and JK Families?
Refer to application note AN-HK-33/H. 1999Oct13 68HC12, 68HC912B32 Serial Communications How can I implement a Distributed Systems Interface (DSI) protocol using the 68HC912B32?
Refer to application note AN1816/D. 1999Oct13 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE Development Tools What is the format of an S-Record?
S-RECORD FORMAT DESCRIPTION
The S-Record format for output modules was devised for the purpose of encoding programs or data files in a printable format for transportation between computer systems.
S-RECORD CONTENT
When viewed by the user, S-Records are essentially character strings made of several fields that identify the record type, record length, memory address, code/data, and checksum. Each byte of binary data is encoded as a 2-character hexadecimal number: the first character represents the high-order 4 bits, and the second represents the low-order 4 bits of the byte.
The 5 fields that comprise an S-Record are shown below:
| TYPE | RECORD | LENGTH | ADDRESS | CODE, DATA | CHECKSUM |
The S-Record fields are composed as follows:
| Field | Printable Characters | Contents |
| Type | 2 | S-Record type - S0, S1, etc. |
| Record Length | 2 | The count of the character pairs in the record, excluding the type and record length. |
| Address | 4, 6, or 8 | The 2-, 3-, or 4 byte address at which the data field is to be loaded into memory. |
| Code, Data | 0 - 2n | From 0 to n bytes of executable code, memory-loadable data, or descriptive information. For compatibility with teletypewriters, some programs may limit the number of bytes to as few as 28 (56 printable characters in the S-Record). |
| Checksum | 2 | The least-significant byte of the one's complement of the sum of the values represented by the pairs of characters making up the record length, address, and the code/data fields. |
Each record may be terminated with a CR/LF/NULL. Additionally, an S-Record may have an initial field to accommodate other data such as line numbers generated by some time-sharing systems. Accuracy of transmission is ensured by the record length (byte count) and checksum fields.
S-RECORD TYPES
Eight types of S-Records have been defined to accommodate the several needs of the encoding, transportation, and decoding functions. The various Motorola upload, download, and other record transportation control programs, as well as cross assemblers, linkers, and other file-creating or debugging programs, utilize only those S-Records that serve the purpose of the program. For specific information on which S-Records are supported by a particular program, the user manual for that program must be consulted.
The important S-record types for 8-bit MCUs are:
S0: The header record for each block of S-Records. The code/data field may contain any descriptive information identifying the following block of S-Records. The address field is normally zeroes.
S1: A record containing code/data and the 2-byte address at which the code/data is to reside
S9: The termination record for a block of S1 records. Address field may optionally contain the 2-byte address of the instruction to which control is to be passed. If not specified, the first entry point specification encountered in the object module input is used. There is no code/data field.
Only one termination record is used for each block of S-Records. Normally, only one header record is used, although it is possible for multiple header records to occur. 1999Oct13 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, 68300, MCORE Serial Communications How can I connect an SCI module to a PC serial port?
Because a Motorola microcontroller and the PC UART work with different voltages, a level translator IC is necessary. A common IC used for this function is the MC145407, which is capable of producing RS-232 voltages from a single 5 V supply. An example circuit is shown here.
1999Oct13
68HC05, 68HC705C8A, 68HC705C9A Serial Communications, General I/O I have an SPI routine that works on the 68HC705C8A, but not on the 68HC705C9A. Why?
The port pins that share functionality with the SPI on the 68HC705C8A are unidirectional, but on the 68HC705C9A they are bidirectional. To use the 68HC705C9A SPI, you must configure the appropriate data direction register bits for that port according to the direction of data flow. Set the DDR bit as an input for the SPI input pin and as an output for the SPI output pin. 1999Oct13 68HC05, 68HC705C8A, 68HC705C9A Clocking My MCU has an RC oscillator option. Should I use it or use an external clock source?
Many Motorola MCUs provide an option for RC clocking that requires no external components or just an external resistor to provide clocking for the MCU. This provides a clock source with a very wide accuracy tolerance. The generated frequency from the same external components can vary in the same MCU from lot to lot, due to process variations.
IMPORTANT: If your application relies on an accurate clock source frequency, DO NOT use the RC oscillator as a clock source.
The oscillator frequency is very sensitive to capacitive loading. Any change in design, especially due to board lay out, device sockets, or conformal coating, can drastically change the resulting RC oscillator frequency.
In cases where wide frequency swings cannot be tolerated, an external clock source should be used. 1999Oct13 68HC08, 68HC908 Timer, General I/O I want to use the output compare in the 68HC08, and have digital control over the associated pin. Can I use the 68HC08 timer module's output compare function without an associated signal on the TCMP pin
Yes, you can use the output compare interrupt in the 68HC08 without placing the associated pin under timer control. Do so by clearing the ELSxB and ELSxA bits. This places the timer pin under port control.
Yes, you can use the output compare interrupt in the 68HC08 without placing the associated pin under timer control. Do so by clearing the ELSxB and ELSxA bits. This places the timer pin under port control. 1999Oct13 68HC08, 68HC908GP32, 68HC908GP20 Memories What are the primary differences in the FLASH between the 68HC908GP20 and the 68HC908GP32?
Yes, you can use the output compare interrupt in the 68HC08 without placing the associated pin under timer control. Do so by clearing the ELSxB and ELSxA bits. This places the timer pin under port control.
Yes, you can use the output compare interrupt in the 68HC08 without placing the associated pin under timer control. Do so by clearing the ELSxB and ELSxA bits. This places the timer pin under port control. 1999Oct13 68HC08, 68HC908GP20, 68HC908GP32 Misc. Besides the FLASH, what other differences are there between the 68HC908GP20 and the 68HC908GP32?
These two devices are intended to be 100% compatible in all regards, except for the size and type of FLASH on board. They have the same modules, the same amount of RAM, same register structure and same pinout and package types. There will be slight variations in current draw, and the user should consult the electrical specifications in the user's manual for the exact range of values. 1999Oct13 68HC08, 68HC908GP32 Memories What supply voltage is required to program the 68HC908GP32?
Programming the 68HC908GP32 can be done at VDD= 5 V or 3 V (+/-10%). If programming in monitor mode and the reset vector is not blank, then a VTST of VDD + 2.5 V to 9 V must be applied to IRQ. Note that VTST does not supply current, it is only a signal that, when present, allows entry into monitor mode. Monitor mode programming is required to disable write protection and is normally not used in circuit. Any block in the 68HC908GP32's FLASH can be write protected in user mode without high voltage. The higher voltage provides an additional precaution to avoiding unintentional write/erase since the write protection cannot be disabled in user mode. 1999Oct13 68HC08, 68HC908GP32 Memories What is the estimated programming time for the 68HC908GP32 FLASH array?
Estimated program time is about 30 uS per byte, or 1 second for the entire 32 K array. This time does not include verification or communication time, which is the bottleneck unless communicating at, or faster than, 115.2 kbaud. 1999Oct13 68HC08, 68HC908GP32 Memories What is the endurance of the FLASH in the 68HC908GP32?
The 68HC908GP32 is specified for 10,000 write/erase cycles over the full operating temperature range of -40 to +85 centigrade. 1999Oct13 68HC08, 68HRC908JL3, 68HRC908JK3, 68HRC908JK1 Memories What is the approximate oscillator frequency that I can expect for a given value of resistance and capacitance used with the 68HRC908JL3, 68HRC908JK3, or 68HRC908JK1?
Using an external capacitor of 10 pF, with VDD = 5.0 V, and operating at room temperature, the RC characteristics of the 68HRC908JL3 are approximately as follows. These values for resulting oscillator frequency are approximate and will vary from part to part. Please consult the data manual for more accurate and/or up-to-date data. Internal frequency will be FOSC/4.
| Resistance/Ohm | FOSC (MHz) |
| 5000 | 14 |
| 5600 | 13 |
| 6200 | 12 |
| 6800 | 11 |
| 7500 | 10 |
| 8200 | 9 |
| 10000 | 8 |
| 12000 | 7 |
| 15000 | 6 |
| 18000 | 5 |
| 20000 | 4.5 |
| 26000 | 3.5 |
| 30000 | 3.0 |
| 39000 | 2.5 |
| 47000 | 2 |
| 56000 | 1.75 |
| 62000 | 1.5 |
| 67000 | 1.4 |
| 70000 | 1.35 |
| 75000 | 1.25 |
| 82000 | 1.15 |
In-circuit programming of the 68HC908GP32 using the PROG08 module of the ICSGP software is done using the following steps. The PROG08 software supports monitor mode communication only. Therefore, the device must be in monitor mode. See the Monitor ROM section of the 68HC908GP32 data book for a description of monitor mode entry requirements. Also, proper clocking of the device must be provided to facilitate an acceptable communication rate. The table labeled 'Monitor Mode Signal Requirements and Options' in the Monitor ROM section specifies under what conditions one can acquire 9600 baud communication.
Note: The 68HC908GP20 and 68HC908GP32 contain a security feature based on information that the user programs to the part. Security bytes are specified in addresses $FFF6 - $FFFD. The PROG08SW software continually records any changes to these security bytes and stores them in the file SECURITY.INI. The information in this file is also shared with P&E's In-Circuit Debugger and In-Circuit Simulator Software. This allows the user to reset the device and still have access to the monitor mode. The PROG08SW software automatically will attempt to access the part by trying the default (nothing written) and up to the last 10 sequences of bytes that have been written to the part. If, after trying each of the sequences of bytes stored in the SECURITY.INI file, the PROG08SW software is unable to access the part, a security dialog box will be displayed which allows the user to specify either the value of these eight bytes or the s record file with which the device is currently programmed.
For a description of how one can prepare a device for re-programming, please see AN-HK-32 -- In-Circuit Programming of FLASH Memory in the MC68HC908GP32. Also see AN-1770 -- In-Circuit Programming of FLASH Memory in the MC68HC908GP20 - for a general discussion of monitor mode entry and FLASH programming. 1999Oct13 MCORE, MMC2001, MMC2003 Memories What are the power connection requirements for the MMC2001 and MMC2003?
The following figure shows the supply voltage ranges required to operate these microcontrollers. To ensure correct microcontroller operation, VDD_IO should be greater than or equal to VDD_CORE and VDD_OSC during a power-up interval.
1999Oct13
MCORE, MMC2001, MMC2003 Memories Does VBATT need to be connected to a power source even if I do not need battery backup?
Yes, a power source must be connected to VBATT whether or not the microcontroller will be battery backed up. VBATT must be at a voltage greater than or equal to 1.8 V and less than or equal to 3.6 V. VBATT can be connected to the VCCE power source (VCCE supply). Please refer to the following figure:
1999Oct13
MCORE, MMC2001, MMC2003 Memories Will all internal RAM/ROM accesses be visible on the microcontroller's external bus when showing internal cycles is enabled?
No. Here is an example where internal RAM/ROM accesses will not be visible on the external bus. If the show enable (SHEN) bits in the external interface module configuration register (EIMCR) are set to 01, show cycles enabled, and the chip select assert (CSA) bit in the pertinent chip select configuration register is set to 1, an idle cycle will be inserted between back-to-back external accesses. Internal RAM/ROM accesses can occur during this idle cycle, but will not be seen on the external bus. 1999Oct13 MCORE, MMC2001 Development Tools Where can I find a copy of the schematic for the MMC2001 development systems, the MMCEVB1200PV, and MMCCMB1200?
The same schematic applies to both the MMCEVB1200PV and the MMCCMB1200 and can be found at:
http://www.mot.com/SPS/MCORE/EVScdrom/
under "M·CORE MMC2001 Evaluation Products", "Schematics".
Because some of the page-to-page signal cross-references on the schematic are difficult to read, the printed wiring board net list for the two development systems is also in that "zip" file. 1999Oct13 MCORE, MMC2001, MMC2003 Development Tools Which debug monitors are present on the MMCEVB1200PV (EVB1200) and MMCCMB1200 (CMB1200) development boards, and how do I select each one?
Mbug resides in ROM on the MCORE microcontroller. Picobug resides in the flash memory on the EVB1200 and CMB1200. With jumper W9 removed, the microcontroller will start executing Mbug from the microcontroller's internal ROM after a hardware reset. With jumper W9 installed, the microcontroller will start executing Picobug after a hardware reset. 1999Oct13 MCORE, MMC2001, MMC2003, MMC2075, MMC2080 Development Tools, Programmer, Program Why won't particular Motorola EBDIs (enhanced background debug interfaces) allow new firmware to be programmed?
A sector of flash memory that the new firmware must be written to was inadvertently write-protected when the EBDIs were manufactured. The sector cannot have the write-protection removed without applying a voltage on one of the pins of the flash memory chip. Please contact Global Data Specialist, 3707 E. Broadway, Phoenix, AZ 85040, (602) 437-4331, for repair or replacement of an affected EBDI. An EBDI connects to an MCORE MCUs OnCE (on-chip emulation) port to 1999Oct13 MCORE, MMC2001, MMC2003 Development Tools, Downloader For the Motorola Flash Programmer downloader utility, can the Communications Protocol selection be changed between flash programmings?
No, the communications protocol selection should not be changed without closing and restarting the utility. The desired protocol can then be selected. 1999Oct13 MCORE, MMC2001, MMC2003 Electrical Specification, Bus Interface, Memories, Wait State, Memory With a CLKIN rate of 32 MHz, can the microcontroller access external SRAM in a single CLKIN cycle?
Presently, no. A CLKIN frequency of 32 MHz corresponds to a cycle period of 31.25 ns. According to specification, CS# can be asserted up to 29 ns into the first clock cycle leaving only 2.25 ns in that cycle for accessing SRAM and for propagation delay from any external logic in series with the CS# signal. At least one wait state should be selected using the chip select configuration register for the chip select concerned. 1999Oct13 MCORE, MMC2001, MMC2003 Development Tools, Bus Interface, Memories, tristate, tri-state, contention Can the address lines on the MCORE microcontroller be set to go into a high-impedance state to allow another bus master to control the address lines (such as for in-circuit programming of a non-volatile
No, the address lines cannot be set to go into a high impedance state. And, driving the microcontroller's address, data, and control lines with another bus master could possibly damage the microcontroller. To in-circuit program a memory device, the address, data, and control lines of the microcontroller could be isolated from the other bus master with external logic. Also, the microcontroller could be commanded through its OnCE debug port to perform the programming operation. Motorola offers an enhanced background debug interface (EBDI), that, used with a personal computer and an appropriate software utility, will control the microcontroller through its OnCE port. With an EBDI, the microcontroller could be commanded to program a non-volatile memory device.
No, the address lines cannot be set to go into a high impedance state. And, driving the microcontroller's address, data, and control lines with another bus master could possibly damage the microcontroller. To in-circuit program a memory device, the address, data, and control lines of the microcontroller could be isolated from the other bus master with external logic. Also, the microcontroller could be commanded through its OnCE debug port to perform the programming operation. Motorola offers an enhanced background debug interface (EBDI), that, used with a personal computer and an appropriate software utility, will control the microcontroller through its OnCE port. With an EBDI, the microcontroller could be commanded to program a non-volatile memory device. 1999Oct13 MCORE, MMC2001, MMC2003 Clocking, LOW_REFCLK, LOW_REFLECK Must an oscillator be connected to the EXOSC and XOSC pins of the microcontroller even if the microcontroller's watchdog, time-of-day, interval timers, and GPIO/keypad are not needed?
Yes, a 32.768 kHz crystal oscillator must be connected to pins EXOSC and XOSC. The oscillator is required in order for the microcontroller to come out of a hardware reset. After power is applied to the microcontroller's VBATT pin, approximately one second ( 215 + 8 ) 32.768 kHz clock cycles must occur before the microcontroller will be allowed to exit the reset state.
Additionally, a supply voltage, VCCI, must be applied to pin X VDD in order to power the 32.768 kHz oscillator. Please refer to the following figure:
1999Oct13
68HC16, 68300 Serial Communications When the pin assignment register, QPAR, assigns a pin to be a QSPI function, is that pin always under control of the QSPI?
No. For a pin to be under the control of the QSPI, two conditions must be met. The first condition is that the selected QSPI pins must be assigned to the QSPI using the QPAR register. The second condition is that the QSPI is enabled, that is, the SPE bit in QSPI Control Register 1 is set to a logic 1.
To send a transmission using the QSPI, the transmit RAM is loaded with the data to be transmitted. Then, the SPE bit is set which enables the QSPI. As soon as the SPE bit is set all pins that are assigned to the QSPI via the QPAR register will be under the control of the QSPI. At the end of the transmission, the SPE bit will automatically clear itself. When the SPE bit becomes a logic 0, all of the QSPI pins will revert to the control of the Port QS Data Register and the Port QS Data Direction Register.
A consequence of the control of the QSPI pins switching between the QSPI and the Port QS Data and Data Direction Registers is that "false" transitions can be created on the QSPI clock line. Take an example where the inactive level of the QSPI clock is low. If bit 2 of the Port QS Data Register is a logic 1 and the Port QS Data Direction Register has made the QSPI Clock Pin, SCK, into an output, the SCK pin will output a logic 1. As soon as the SPE bit is set, the SCK pin will switch to the control of the QSPI. As our example calls for the resting level of the clock to be a logic 0, the SCK line will take a logic 1 to logic 0 transition when the SPE bit is set. To all of the SPI devices connected to the QSPI, it will appear as though they have just received a valid clock edge which is not the case. The peripherals will have received an "unintended" transition. When the QSPI disables itself by clearing the SPE bit, a second "unintended" transition will occur. This, of course, will totally unsynchronize QSPI transmissions. The solution to this problem is to make sure that the Port QS Data Register is properly programmed to prevent these "unintended" transitions. In the present case, the data register bit for SCK should always be the same as the resting or inactive level of the SCK line. 2000Jan28 68HC16, 68300 Serial Communications When using the QSPI on MC68HC16 and MC68300 microcontrollers, does the setting of the SPIF bit indicate that the current transmission has completed?
No. The SPIF bit indicates that the last byte in the QSPI transmit RAM has been loaded into the QSPI shifter. The setting of the SPIF bit indicates to the CPU that new data can be written to the QSPI transmit RAM
In some cases, programmers have cleared the SPE bit with their software as soon as the SPIF bit sets. This will truncate the last transmission of the QSPI.
The proper method to disable the QSPI is to monitor the SPE bit. This bit will automatically clear itself. When this bit clears, the current transmission plus a programmable delay time will be finished and there will not be a problem with changing the function of the QSPI or starting another transmission.
Once again, the QSPI will be active until the SPE bit self clears. No attempt should be made to reprogram the QSPI registers or transmit / receive RAM until the SPE bit self clears. 2000Jan28 68HC16, 68300 Bus Interface What can cause the external BU to stop running bus cycles on a SCIM basded MCU?
One cause for the external bus to stop running bus cycles is that the Bus Grant Acknowledge has floated or been driven low. The Single Chip Integration Module (SCIM) can operate in the Single Chip, 8-Bit Expanded and 16-Bit Expanded Bus Mode. In the Single Chip and 8-Bit Expanded modes, the Bus Grant Acknowledge pin always performs the BGA function at the release of reset. In the 16-Bit Expanded Mode, the Bus Grant Acknowledge pin will perform the BGA function if Data Bus 10 is high at the release of Reset. If the BGA pin is either pulled low or floats low, the external but will halt immediately.
To prevent the errant condition from occurring, a pull up resistor must be used to pull the BGA pin to a logic 1. This problem is temperature dependent. Also, if BGA is floating, capacitive coupling between the BGA pin and another board trace can cause the BGA pin to float low. This problem can appear to be software related as the software can cause certain "patterns" to be driven on the address and data busses that will be more prone to pull floating pins one way or another. However, any connection between the BGA pin floating to a logic 0 and the software that is running is simply coincidental.
Always put a pull up resistor on the BGA pin. 2000Jan28 68HC16, 68300 Bus Interface If DSACK is grounded on a 68300 MCU, will all external bus cycles take three system clocks?
No. In general, grounding the DSACK lines to give either an 8-bit DSACK or 16-bit DSACK will cause an external memory cycle to take three clock cycles. In some board level designs the system designer depends upon all external memory accesses to be exactly three clock cycles. By assuming that all external memory accesses are three cycles, the board designer can incorrectly design a board such that two three-clock cycle accesses could be run back to back.
In the CPU32 design, a normal three-cycle bus access can be extended by one clock cycle when an op code prefetch occurs on the first cycle of an Interrupt Acknowledgement Cycle.
This extra cycle will generally have no affect that can be detected by the user or the system hardware or software. However, in the case where the board designer was depending upon back to back three cycle memory accesses, memory corruption can occur because a memory cycle took an extra cycle.
To compensate for the problem of an extra clock cycle on certain external bus cycles, any external memory controllers should wait for the de-assertion of either Data Strobe or Address Strobe before allowing the next memory cycle to begin.
Conclusion: When designing an external memory controller, make sure that the current memory cycle has completed by observing the de-assertion of AS or DS before starting the next memory cycle. 2000Jan28 68HC16, 68300 Clocking What can cause clock drift at elevated temperatures on 68HC16 and 68300 Family devices? On modular products, some engineers observe that the Clock Out pin begins to drift off frequency as the temperature increases. This problem is generally seen at system clock frequencies above 18 MHz. Usually the observed frequency varies from the desired frequency by 2 or 3 Megahertz.
The general cause of this problem is that the VCO is operating at a frequency that is out of spec. The maximum frequency for the VCO is two times the maximum rated frequency of the device. That is, a 16.7 MHz part would have a maximum VCO frequency of 33.4 MHz, a 20.9 MHz device would have a maximum VCO frequency of 41.8 MHz and so on.
When a modular device first powers up, the VCO will be operating at 4 times the system clock frequency. Thus, if the device has a system clock of 8.38 MHz the VC0 frequency is 33.52 MHz which is within the electrical specifications of the part.
If an attempt is made to run a device rated at 16 MHz with a system clock speed greater than 8 MHz, the Clock Synthesizer Control Register must be properly programmed such that the maximum VCO speed is not exceeded.
To do this, the "X" bit in the SYNCR register must be set to a logic 1. This bit controls a divide by 2 circuit which sits between the output of the VCO and the Intermodule Bus Clock line. This divide by 2 circuit does not sit inside the feedback path of the PLL/VCO. By setting the X bit to a logic 1, the divide by 2 circuit is bypassed which will cause the VCO frequency to only be two times the system clock speed instead of the 4 times speed. With the X bit set to a logic 1, a system clock speed of 16.7 MHz can be obtained while running the PLL/VCO at 33.52 MHz which is within the electrical specifications. 2000Jan28 68HC16, 68300, MPC500 Timer Does the TPU (Time Processor Unit) parameter RAM have to be written as words or on word boundaries?
Yes. The TPU parameter RAM is composed of 16-bit words. The TPU Parameter RAM can be read as bytes. However, writing the TPU Parameter RAM as bytes can cause problems. If the lower byte of a TPU Parameter RAM location is written with a "byte wide" access, the upper byte of the TPU Parameter RAM location will be written to $FF. Depending upon how the TPU Parameter RAM is used, this particular feature may or may not cause a problem with the system software.
However, it is highly recommended that all accesses to the TPU Parameter RAM be word wide accesses on word boundaries to prevent any possible corruption of the RAM. 2000Jan28 68HC16, 68300 Clocking What are the correct VCO/PLL FILTERS VS. MASK SET for MC68HC16 and MC68300 Family devices?
The following table is a list of various MC68HC16 and MC68300 Family devices that show which mask sets use either the Normal Stability Operating Environment Filter (Fig. 1) or the High Stability Operating Environment Filter Circuit (Fig. 2). It is important to use the proper filter with each mask set. Using the Normal Operating Environment Filter on microcontrollers that require the High Stability Operating Environment filter may result in excessive jitter in the system clock frequency. Using the High Stability Operating Environment Filter on microcontrollers that require the Normal Operating Environment filter may prevent the microcontroller from coming out of reset.
MC68HC16P3
Normal
High Stability
MC68HC916P1
Normal
High Stability
MC68HC916R1
Normal G72C
High Stability None
MC68HC16R3
Normal H34K
High Stability
MC68HC916R3
Normal H70E
High Stability
MC68HC16V1
Normal E47W, F33P, G87B
High Stability
MC68HC916X1
Normal
High Stability H97A
MC68HC16Y1 MC68HC916Y2 MC68HC16Y3 MC68HC916Y3 MC68HC916Y5 MC68HC16Z3 MC68HC16S2 MC68CKZ1 MC68CMZ1 MC68HC16Z1 MC68HC16Z2 MC68HC16Z4 MC68332 MC68F333 MC68334 MC68335 MC68336 MC68338 MC68376 The following information also applies to the L, C and CK versions. On the 144 pin PQFP package for the MC68331 and MC68332, pin 106 is PE5/AS. On the 132 pin PQFP package for the MC68331 and MC68332, pin 82 is PE5/AS. View CPU16 Instruction Flow. 2000Jan28
68HC16, 68300 Exceptions Is it possible for a "Write $55, Write $AA" reset sequence to fail to reset the Software Watchdog Timer? YES. The software watchdog on MC683xx and MC68HC16 devices is used to detect improperly operating software. The software watchdog is enabled from the release of external reset. That is, the SWE bit (bit 7 of the system protection control register at $xxFA21) is set to a logic 1 automatically. The software watchdog counter will be reset to its maximum value when the system software writes the value $55 followed by $AA to the software watchdog service register (SWSR) at $xxFA27. If the software watchdog is not reset at appropriate intervals, it will decrement to $0000 and cause a software watchdog reset which is equivalent to a hardware reset. There are some hardware considerations that limit the rate at which software watchdog reset sequences can occur. Specifically, when a write $55, write $AA sequence is written to the SWSR, the actual reseting of the software watchdog counter does not occur until the next falling edge of the software watchdog clock. Once the software watchdog counter reset sequence is performed, further attempts to perfom either a software watchdog reset sequence or change the software watchdog time out period are inhibited for the clock low time of the software watchdog clock period immediately following an actual reset of the watchdog counter. Therefore, for proper and predictable operation of the software watchdog, do not update the SWSR at a rate which is more often than twice the period of the software watchdog counter clock source. 2000Jan28
68HC908GP32, 68HC908GP20, 68HC08 Development Tools Can I use my existing 68HC908GP20 development tools to develop for the 68HC908GP32? If you have the M68ICS08GP20 In-Circuit Simulator Development kit, go to http://www.pemicro.com/hc08 for a software upgrade to support the 68HC908GP32. If you have the M68EML08GP20 emulation module for the MMEVS (KITMMEVS08GP20) or MMDS (KITMMDS08GP20), go to http://www.mcu.motsps.com/dev_tools/emconfig.html to download updated configuration files. The M68EML08GP20 emulation module will correctly emulate the 68HC908GP32 with the M68TC08GP20FB44 and M68TC08GP20P40 target head adapters only. Do not use the M68TC08GP32FB44 (for QFP), M68TB08GP32P40 (for DIP), or M68TB08GP32B42 (for SDIP) target head adapters as these work only with the M68EML08GP32 emulation module. While it is not required, the 68HC908GP20 CPU installed on the M68EML08GP20 may be replaced with a 68HC908GP32. If you have a third party development tool contact the tool provider for upgrade information. 2000Jan28
68HC908GR8, 68HC908KX8, 68HC908JL3, 68HC908JK3, 68HC908JK1, 68HC908JB8, 68HC08 Memories How do I use the on-chip programming routines? Refer to application note AN1831/D. 2000Feb01
68HC908AZ60, 68HC08 Memories, Controller Area Network (CAN) How do I program the 68HC908AZ60 via the CAN interface? Refer to application note AN1828/D. 2000Feb01
68HC908AS60, 68HC08 Memories How do I program the 68HC908AS60 FLASH? Refer to application note AN1827/D. 2000Feb01
68HC705, 68HC05, 68HC908, 68HC08, 68HC11, 68HC711, 68HC12, 68HC912 Serial Communication How do I communicate using I2C using software bit banging? Refer to application note AN1820/D. 2000Feb01
68HC908, 68HC08, 68HC705, 68HC05 Serial Communication How do I implement a software SCI (UART) by using a 16-bit timer? Refer to application note AN1818/D. 2000Feb01
MCORE, MMC2001, MMC2003 Development Tools How do I communicate through the MMC2001/2003 OnCE Port? Refer to application note AN1817/D. 2000Feb01
68F375, 68300 Memories, Controller Area Network (CAN) How do use the QADC64 module on the 68F375? Refer to application note AN1791/D. 2000Feb01
68300, HC16, MPC500 Timer, Misc. Considerations for clearing the "Match Recognition Latch" and writing the "Match Event Register" in TPU Microcode. A problem that can occur when writing TPU microcode is that an input channel will fail to recognize incoming edges. Manytimes, the symptom will be that the first incoming edge is recognized but no edges are recognized on a channel after that. Executing the same microcode on another channel will sometimes solve the problem. This problem has been observed on about 1 out of each 10,000 units. This problem can possibly occur when the following conditions are met: Normally, the "write_mer" would cause a match event to be scheduled in the future, thus preventing a match from occuring immediately. However, a "write_mer" by itself in the last instruction of the state under the conditions described above can, under rare occassions, cause the Match Recognition Latch which was set in the current TPU state to be recognized as a new match and cause a "request for service". In general practice, include "neg_mrl" with a "write_mer". The Load Floating Point Single Precision instruction is used to fetch a floating point single precision number from an Effective Address. The number is converted to floating point double precision and placed in a floating point register, frD. If the single precision number is out of range, a floating point assist exception will be taken. The number will not be converted to double precision nor will any results be written into the destination register for the instruction. Recall that the range of operands for the LFS instuction is 2-126 to 2E128 - 1. If the operand of the LFS instruction is between 2-150 to 2-126, a Floating Point Assist Exception will be taken. Some programmers have interpreted the LFS instruction to take any single precision floating point number, even if the number is out of range as described above, convert it to double precision and then load the result into the destination register. The instruction does not work this way. 2000Apr25
MPC500 Memories CONSIDERATIONS FOR PROGRAMMING AN MPC500 WITH AN ERASED FLASH When an MPC555 (Rev. K or later) or any MPC500 family derivative is totally erased, the CMFCFIG (shadow row location 0) and the flash array will be erased. In this condition, the Flash Array and the Shadow Row 0 Bits must be programmed. This programming proceedure is generally done through the BDM port. In order to properly initialize the device so that the BDM port is enabled, a Configuration Word must be supplied from some source. The sources are: If the RSTCONFIG pin is driven to a logic 1, thedevice will attempt to use the Default Configuration Word or the CMFCFIGfor the Configuration Word. If the CMFCFIG Bits are erased and RSTCONFIG = 1,the Has Configuration bit will indicate that no ConfigurationWord is available from CMFCFIG. Therefore, only the Default ConfigurationWord of 0x00000000 can be used. If the RSTCONFIG pin is driven to a logic 1 and the Has Configuration bit indicates that the CMFCFIG does contain the configuration information, the Configuration Word would come from the CMFCFIG. When using the Default Configuration Word of $00000000, the Flash Array will be disabled. However, the BDM port will be enabled. This does not mean that the Background Mode has been entered, it means that it is possible to enter the Background Mode. If the BDM mode is not enabled after the release of Reset, the Background Mode cannot be entered later. The BDM tool can run a macro to enable and enter the BDM mode. If the flash is not enabled by the Reset Config Word (Bit 20 = 1 of external Config. Word or Bit 20 = 0 of Flash Shadow Reset Config), the flash must be enabled by ORing $800 into the IMMR SPR 638. This enables the flash and it will be available for programming. 2000Apr25
MPC500 Clocking, Exceptions BEHAVIOR OF CLOCK OUT ON THE MPC 555 DURING RESET The Clock Out Pin of the MPC555 behaves in the following way under various reset conditions: Ascent Technologies does training for most of Motorola's microcontrollers. They can be reached at . 2000May2
68300, HC16 Misc., General I/O, Bus Interface Can Single Chip Integration Module(SCIM) chip select lines be programmed to respond to data space and/or program space? Yes, this programming is possible. It has been a misconception that the Chip Select lines on the SCIM (Single Chip Integration Module) used on the MC68300 and MC68HC16 families of microcontrollers can only be programmed to assert on Supervisor Space Only, User Space Only, Supervisor and User Space or CPU Space. The chip select lines have additional flexibility. MC68300 CPU Space Chip Select Settings User Program Space (Supervisor and User) Program Space This programming is accomplished in the following way. When the SPACE FIELD of a Chip Select Option Register is programmed to %00, the IPL field specifies which interrupt level will be used to make the associated CS line assert during an IACK cycle. However, if the SPACE FIELD of a Chip Select Option Register is programmed to %01 (USER), %10 (Supervisor) or %11 (Supervisor and User), the IPL field encoding takes on a different meaning. The codings are as follows: %000 - Data/Prog Space, %001 - Data Space, %010 - Program Space, %011 and %100 are reserved for future use, %101 - Data Space, %110 - Program Space, and %111 is reserved for future use. HC16 CPU Space Chip Select Settings(Note: CPU16 supports only SUPERVISOR SPACE and not USER SPACE.) This programming is accomplished in the following way. When the SPACE FIELD of a Chip Select Option Register is programmed to %00, the IPL field specifies which interrupt level will be used to make the CS line assert during an IACK cycle. However, if the SPACE FIELD of a Chip Select Option Register is programmed to %10 Supervisor or %11 Supervisor, the IPL field encoding takes on a different meaning. The codings are as follows: %000 - Data/Prog Space, %001 - Data Space, %010 - Program Space, %011 and %100 are reserved for future use, %101 - Data Space, %110 - Program Space, and %111 is reserved for future use. While this data is presented in the SCIM USERS MANUAL (Single Chip Integration Module - document # SCIMRM/AD), it is being repeated here for clarity and emphasis. 2000May02
MPC500, 68300, 68HC16 Timer How do I run the PWM and QOM functions on the MPC555 TPU3, and are there SW examples? The following code snippet is used to generate PWM functions on TPU A channels 15 and 0, and TPU B channels 15 and 0. The snippet also runs the QOM function on TPU B channel 10. The QOM function is programmed to continuously output a wavefore with six different periods. The first period is 400 TCR1 counts high, 200 TCR1 counts low, 100 TCR1 counts high, 100 TCR1 counts low, 200 TCR1 counts high and 400 TCR1 counts low. The six periods are defined in TPU A channel 10 Parameter RAM locations 0x 0030 41A4 - 0x 0030 41AE. --------------- ---- -------- --- The PWM functions are programmed to output a continuous PWM signal. The high times and periods of the PWMs are programmed into the 3rd and4th parameter RAM locations of their respective channel’s parameter RAM. For more information, see TPUPN17/D and TPUPN01/D for the PWM and QOM functions, respectively, of the Time Processor Unit (TPU). Main.c contains the C source code and can be found in qom_pwm.c. 2000May09
68HC705, 68HC05 Exceptions Is it necessary to perform double reset wih 705B16 or 705B16N? Yes. To insure correct operation of the 705B16 after power-on, the device must be reset a second time after power-on. It can be done in software using the 705B16 watchdog. It would be same as any pull-up resistor, which in this case would be 45 K( Please refer to The answer is indeterminate. However, in general, simply stopping the clock will NOT put the part in a state with the lowest power consumption. In order to get the STOP mode current, a STOP instruction must be executed. Particularly in the older HCMOS designs, the software tools for finding "floating nodes" and "driver conflicts" did not exist. Therefore, it is possible in parts designed before these tools were available to still have some floating nodes. A floating node will cause unwanted current consumption. To restate, the only way to guarantee STOP MODE current is to execute a STOP instruction. Stopping the clock is NOT guaranteed to produce a state that will give STOP mode current. 2000Jun22
68HC16, 68HC916, 68300, MPC500 Timer What is the proper procedure to initialize/change modes of a DASM Channel in the Configurable Timer Module( CTM )? To use a DASM(Double Action Submodule) channel of the Configurable Timer Module(CTM) in the OPWM mode, it is imperative that all registers for the function be initialized with the DASM channel operating in the DIS(Disable) mode. Failure to properly initialize the part can result in invalid and unexpected output compare and input capture results and flags being set incorrectly. After initializing the DASM channel's associated registers, the DASMISC register can be programmed to select the OPWM mode. The proper method for using the DASM function is to select the DIS mode. Then, initialize the associated registers. Once this is done, the DASM Status/Interrupt Control Register can be written. The FORCE A and FORCE B bits and the MODE bits of this register are used to force the output of the DASM channel to a predefined state and at the same time enable the desired mode of operation. Failure to follow this procedure can randomly cause the output of the DASM channel to remain permanently high or permanently low. To restate, when using the DASM channel in the OPWM mode: No. In order to enter forced monitor mode, it requires either Vdd on /IRQ & /RST or Gnd on /IRQ and Vdd on /RST depending on your oscillator.See Table 15-1 on page 199 of the MC68HC908GP32 Technical Data Manual(MC68HC908GP32 Technical Data ). The M68ICS08GP development tool drives both of these signals to Vtst. 2000Jul26
68HC08, 68HC908 Exceptions, CPU, Instructions How are the security bytes for the HC908's determined? The data stored in the interrupt vectors at $FFF6 - $FFFD comprises the security bytes. 2000Jul26
68HC08, 68HC908 Development Tools, Memories Is it possible to perform in circuit programming on the MC68HC908JL/JK parts with low programming voltage(5 V) and just two connections? Yes. The part must be blank (erased) and you must use an appropriate oscillator to get a working baud rate. Use the J2 connector on the ICS, which uses only the Gnd and PTB0 connections. 2000Jul26
68HC08, 68HC908 Tools, Misc. Is it possible to enter forced monitor mode (blank part, no high voltage on /IRQ) using the M68ICS08MR in circuit simulator? No. In order to enter forced monitor mode, it requires Vdd on /IRQ & /RST. The M68ICS08MP drives both of these signals to Vtst. 2000Jul26
68HC08, 68HC908 Clocking, Development Tools Which pin on the MC68HC908GP32 determines the oscillator divisor while in normal monitor mode? The PTC3 pin determines if the external oscillator frequency is divided by two or four to drive the internal bus frequency. If PTC3 is low, the external oscillator frequency is divided by two. If PTC3 is high, the internal bus frequency is 1/4 of the external oscillator frequency. 2000Jul26
68HC08, 68HC908 Clocking, Development Tools Which pin on the MC68HC908JL/JK determines the oscillator divisor while in the normal monitor mode? The PTB3 pin determines if the external oscillator frequency is divided by two or four to drive the internal bus frequency. If PTB3 is low, the external oscillator frequency is divided by two. If PTB3 is high, the internal bus frequency is 1/4 of the external oscillator frequency. 2000Jul26
68HC08, 68HC908 Clocking, Development Tools Which pin on the MC68HC908MR32 determines the oscillator divisor while in the normal monitor mode? The PTC2 pin determines if the external oscillator frequency is divided by two, or four to derive the internal bus frequency. If PTC2 is low, the external oscillator frequency is divided by two. If PTC2 is high, the internal bus frequency is 1/4th of the external oscillator frequency. 2000Jul26
68HC08, 68HC908 Development Tools, Misc. On the HC908's, what is the difference between Normal Monitor Mode and Forced Monitor Mode? Forced monitor mode requires that the Flash in the MCU be blank(erased state) and no high programming voltage (Vtst) is required on the /IRQ pin. The normal monitor mode requires a high voltage (Vtst) on the /IRQ pin and other I/O pin conditions must be met (see monitor mode entry table requirements in the Technical Data Manuals for the particular part you are using). 2000Jul26
68HC08, 68HC908 Clocking, Development Tools Is it possible to change the divisor that determines the relationship between the external oscillator and the internal bus frequency, of the MC68HC908GR8, in normal monitor mode? No. The relationship is fixed to a divide by 4. The internal bus frequency will be 1/4 of the external oscillator frequency. 2000Jul26
68HC08, 68HC908 Clocking, Development Tools Is it possible to change the divisor that determines the relationship between the external oscillator and the internal bus frequency, of the MC68HC908KX8, in normal monitor mode? No. The relationship is fixed to a divide by 4. The internal bus frequency will be 1/4 of the external oscillator frequency. 2000Jul26
MCORE Serial Communication, Electrical Specification Is a pull-up resistor required for the SPI_EN on the ISPI of the MMC2001? Yes. The documentation for the DRV bit of the ISPI Control Register says that this bit is normally used to configure the SPI_CLK, SPI_EN and SPI_MOSI pins as either "open-drain" or totem pole outputs. The DRV bit actually only works correctly for the SPI_CLK and SPI_MOSI pins. The SPI_EN bit always operates in the "open-drain" mode! If one wants an active LOW on the SPI_EN pin, a light external pull-up is required, 10k is sufficiant. If one wants an active HIGH on the SPI_EN pin, an external pull-down is required. As an additional note, the SNS bit and the SPI_EN bit should always be the same value. 2000Jul31
68HC08 Serial Communication, Misc. Where can i get the application note software for AN1748('Building a Universal Serial Bus Keyboard Hub Using the Motorola MC68HC(9)08KH12') that is listed on page 23)? Please go to the link () and down load the software (/a,Keyboard Hub). 2000Aug02
68HC08 Clocking What frequency must I use to calculate the PLL frequency on the HC908AB? The Frequency fNOM on pages 99 and 103 in section 2.3.2.1 and 2.3.2.4 is 4194 MHz, the Frequency fNOM at page 317 in section 23.10.1 is 49152 MHz. The fNOM is 4.9152Mhz. The MC specification has been corrected. 2000Aug02
68HC08 Clocking, Analog If using the MC68HC908MR24 and pairing the PWM outputs so they are the inverse of each other, and after setting the dead time, how can an A/D reading be timed to take place directly after the low side PWM output goes high? The A/D on the MC68HC908MR family can not be triggered by the hardware on the PWM module. The MR family A/D's are triggered just like those on the MC68HC05P, etc. family. 2000Aug02
68HC08 Memories, Development Tools Is there a programmer that will program multiple MC68HC908GP32xxx at the same time? We have a gang programmer. Please find the part # below: The gang programmer platform board M68HC705UGANG and adaptors for different packages are: Maximum 10 adaptors can be put on the platform board. It is a stand alone programmer, not PC connection. You need to program the customer code into a EPROM first. The gang programmer will then read the data from the EPROM and program it into the GP32 MCUs. 2000Aug02
68HC08, 68HC05 Misc. Please clarify what "patented dead-time compensation" is when referring to PWM signals. The dead-time insertion causes distortion in the sinsusoidal voltage and current waveforms. The distortion correction function compensates for this by automatically *adjusting* pwms to yield a much cleaner sine shaped voltage and current waveform. ()AN1728/D,Making Low-Distortion Motor Waveforms with the MC68HC708MP16 discusses this function. 2000Aug02
68HC08 General I/O, Timer What happens to the port D(fault pins) on the HC908MR family when the PWMs are enabled? Is there a way to *disconnect* the fault pins from the PWM unit so it can be used as general inputs? The fault pins cannot be disconnected from the PWM outputs. This was done for regulatory safety reasons. Many (if not most) of the regulatory agencies take a dim view of systems where fault protection can be disabled by software. 2000Aug02
68HC08 Clocking, Serial Communication On the MC68HC908GP32, what are my options for crystal frequencies and baud rates while in the monitor mode? Divide by 2 option (PTC3 driven by ICS or Vss): Divide by 4 option (PTC3 at Vdd): Divide by 4 option (PTB3 at Vdd): Divide by 4 option (PTC2 at Vdd): No. The Flash does not require a high voltage for programming. However, if the part has been previously programmed, a high voltage is required on the /IRQ pin to place the part into monitor mode. This high voltage has nothing to do with the Flash programming. It is used to put the part into monitor mode once the reset vectors have been programmed. 2000Aug14
68HC08 Memories How can I reprogram an HC08's Flash without using the monitor mode? You can reprogram in the application programming. This can be done by loading new user vectors and a new user monitor at the end of the Flash array. Use the SCI port to communicate to the part rather than PTA0. Remember to program the Flash Block Protection Register to protect the new monitor and vectors. Also note that since you are protecting part of the Flash array, you can no longer perform a bulk erase. 2000Aug14
68HC08 Memories Can the Flash in the HC08's be used as EEPROM? Yes. Use a method where each time you write data to the Flash, you use a different portion of the page (128 bytes). When this page is full, perform a page erase. By doing this, it will only count as 1 program erase cycle (Flash is guaranteed for 10,000 program erase cycles). To extend this even further, use multiple pages. 2000Aug14
68HC16, 68300 Timer Is the PTP bit of the Periodic Interrupt Timer Register a "Write Once" bit? In most cases, yes. The PTP bit is located in the Periodic Interrupt Timing Register at location $YFFA24. (Y is not used for the M68HC16 and should be treated as though it were an $F. Y can be $7 or $F for the M68300 family depending upon the setting of the MM bit in the Module Configuration Register of the SIM or SCIM.) It is used to either enable or disable a "divide by 512" prescaler for the Periodic Interrupt Timer (PIT). In the early versions of the M68300 and M68HC16 families, the PTP bit could be written at any time. However, the functionality of the bit has changed. On virtually all M68300 and M68HC16 family members, the PTP bit has been changed to a "write once" bit. For all future designs with either of these microcontroller families, the PTP bit should be treated as a "write once" bit. 2000Aug15
68HC16, 68300 Serial Communications, Exceptions Does the Serial Communications Interface and the Serial Peripheral Interface share the same interrupt vector? NO. In the QSM the interrupt vector number is written into the QILR-QIVR register at $FF FC04. The default value for this register is $000F. $F specifies the Uninitialized Vector in the Interrupt Vector Table. When initializing the INTV field, it is important to realize that bit 0 is actually ignored. When the SCI causes an interrupt, bit 0 of the QILR-QIVR register will be read as a logic 0. When the SPI causes an interrupt, bit 0 of the QILR-QIVR register will be read as a logic 1. Assume that the vector number 64 (Vector Offset = $100) is written to the INTV field. Then the SCI would use vector number 64 (Vector Offset = $100) and the SPI would use vector number 65 (Vector Offset = $101). However, the same results would be obtained if the vector number 65 (Vector Offset = $101) is written to the INTV field. Once again, the SCI would use vector number 64 (Vector Offset = $100) and the SPI would use vector number 65(Vector Offset = $101), not vector number 66(Vector Offset = $102). Once again, the QSM hardware drives bit 0 of the INTV field. Bit 0 of the actual register is ignored. The consequences of writing vector number 65 to the INTV field is that the software writer may assume that vector numbers 65 and 66 are being used. The fact is that vector numbers 64 and 65 will be used. When this particular programming error is made, i.e., using an odd number in the INTV field, the SCI will appear to take the wrong vector. 2000Aug15
68HC12 Exceptions Where are the interrupt vectors located for the MSCAN on the HC912BC32? The interrupt vector locations for the MSCAN on the MC68HC912BC32 are:
Normal D34F, D16P, D38W, D57W, E72G, F94C
Normal E41C
High Stability
Normal E83M
High Stability
Normal F83C
High Stability None
Normal G45B, F43K
High Stability
Normal
High Stability
Normal G26C
High Stability H32H
Normal G12C
High Stability None
Normal H29C, H69J
High Stability
Normal H29C, H69J
High Stability
Normal H29C, H69J, D35C, D12N, E45F, E62W, E69W, E54F, F73T, F67V,
High Stability
Normal D55T, E34C, E11P, G11D
High Stability
Normal H63H
High Stability H93K
MC68331
Normal C47T, E93N, E95B, F43E, G91H, H17A
High Stability
Normal B30G, C81F, C32J, C17P, C53T, D88A, D33F, D87M, E38R, F78A, F98R, G10K, G30S
High Stability J66A, J30C
Normal C37T, D59N, E66B, F48H, F34W, G50G
High Stability G21R,
Normal D79M,
High Stability E45M, F44N, G38F
Normal E97F, F60G, G88E
High Stability H12J
Normal D36J, D65J
High Stability F60K, F70K
Normal F84R, G44C, G86F, G88T, H99D, H17D, G88T, H17D
Normal F63B, F68G, G70J, H57P
High Stability
Normal
High Stability F66K, F71K 2000Jan28
68HC16, 68300 General I/O What are the correct pin outs for the AS and DS pins on the MC68332 and MC68331?
On the 144 pin PQFP package for the MC68331 and MC68332, pin 110 is PE4/DS.
On the 132 pin PQFP package for the MC68331 and MC68332, pin 85 is PE4/DS. 2000Jan28
68HC16 CPU, Development Tools How to track program execution through the CPU16 using IPIPE and IFETCH?
When the above conditions are met the following errant behavior can occur on about 1 out of 10,000 units. With matches disabled inside the state, a match event will not cause a Request For Service to be generated although the match event will cause the Match Recognition Latch to be set. When a "write_mer" occurs in the last statement without a "neg_mrl", the "end of state" can cause the Match Event Latch to get recognized and cause a Request For Service before the "write_mer" sets up a new match.
If a "write_mer" occurs in the last instruction of a state, always include a "neg_mrl" in that instruction. 2000Mar28
MPC500 CPU, Instructions, Exceptions Floting Point Assist Exceptions on LFS instruction on MPC500 devices
If the RSTCONFIG pin is driven to a logic 0, the devicewill use the External Configuration Word.
Once the device is running code, an HRESET can occur. The CLOCKOUT pin will continue to run at the frequency it was running at when the HRESET occurred and will continue to be driven out the Clock Out pin. HRESET does not affect the PLL prescaler bits. 2000May1
MCORE, MPC500, HC16, HC12, HC11, 68300 Misc. Where can I find information about Motorola Microcontroller training classes? Supervisor Program Space
Supervisor Data Space
Supervisor (Program and Data) Space
User Data Space
User (Program and Data) Space
(Supervisor and User) Data Space
(Supervisor and User) (Program and Data) SpaceSupervisor Program Space
Supervisor Data Space
Supervisor (Program and Data) Space
QOM Output in TCR1 clock periods
| | | | | | |
| | | | | | |
--- -------- ---- ---------------
400 200 100 100 200 400
2000May11
68HC908, H68HC08 Electrical Specification, Exceptions What is the pull-up resistor value for IRQ1 on the 908GP32?
The following sub-routine should be used:
RESET2:
BSET 0, $0C ;Start watchdog
STOP ;causes immediate watchdog
The interrupt vector at $3FF0 and $3FF1 must be initialised with theRESET2 address value( Please refer to Section E-1 Rev. 4 for more informationMC68HC05B4/705B5/05B6/05B8/(7)05B16/705B16N/(7)05B32 Technical Data ).
When using 705B16N reset twice in not required. The interrupt service routine for the vector at address $3FF0-$3FF1 is no longer required,as the vector will never be fetched( Please refer to Section F-1 Rev. 4 for more information MC68HC05B4/705B5/05B6/05B8/(7)05B16/705B16N/(7)05B32 Technical Data ).
page 374 in MC68HC908GP32 Technical Data for reference ). 2000Jun15
68HC705, 68HC05 Electrical Specification When an external clock is driving the EXTAL pin of an MC68HC05, will the device draw "stop mode" current when the clock is stopped?
2000Jul06
68HC08, 68HC908 Development Tools, Misc. Is it possible to enter forced monitor mode (blank part, no high voltage on /IRQ) using the M68ICS08GP in circuit simulator? 40 DIP-P M68UPA08GP32P40
44 QFP-FB M68UPA08GP32FB44
42 SDIP-B M68UPA08GP32B42
2000Aug14
68HC08 Clocking, Serial Communication On the MC68HC908/JK1/JK3/JL3, what are my options for crystal frequencies and baud rates while in the monitor mode?
Divide by 2 option (PTB3 driven by ICS or Vss):
2000Aug14
68HC08 Clocking, Serial Communication On the MC68HC908MR32, what are my options for crystal frequencies and baud rates while in the monitor mode?
Divide by 2 option (PTC2 driven by ICS or Vss):
2000Aug14
68HC08 Clocking, Serial Communication On the MC68HC908GR8, what are my options for crystal frequencies and baud rates while in the monitor mode?
2000Aug14
68HC08 Clocking, Serial Communication On the MC68HC908KX8, what are my options for crystal frequencies and baud rates while in the monitor mode?
2000Aug14
68HC08 Memories Is a high programming voltage required to program the Flash on an HC08?
