Hardware Reference Manual January 11, 1994 $Source: /u/cyliax/Projects/MC68030/Doc/Manual/hardware.ms,v $ Introduction This is a very preliminary Hardware Reference Manual for the IU-CS workstation. It describes the motherboard hardware and monitor software. 1. General Description The IU-CS workstation is a 68030 based workstation with PC compatible ISA bus. 1.1. System Configuration A typical system would conist of some or all of the following components: 1. Motherboard 2. VGA card 3. Multi-IO card 4. Floppy drive 5. Hard disk 6. PC-AT compatible Keyboard 1.1.1. Mother-board The mother-board contains the CPU, the memory and the PCbus slots for add-on peripherals. It also has a MFP (Multi-Function-Peripheral) chip, to which the keyboard con- nects. Although a minimal system could be build without PCbus cards, it wouldn't have any method to communicate. 1.1.2. VGA Card A VGA card can used for the console display in conjunc- tion with a PC-AT compatible keyboard. If no VGA card is sensed by the monitor, the first serial port will be used for the console. Currently, the monitor only supports VGA cards that are compatible with the Western Digital (WD90C00) or Paradise (PVGA1A) chip sets. 1.1.3. Multi-IO Card A PCbus multi-IO card provides the system with a floppy, hard disk, serial and parallel ports. Most also have a game port, which is not used by the monitor. The monitor January 11, 1994 - 2 - supports serial ports from COM1-COM4 and floppy drives on A: as well as IDE hard drives. 1.1.4. Floppy Drive Any PC compatible floppy drives can be connected, although the monitor currently only supports booting from 720kb 3.5" floppies. 1.1.5. Hard Disk Any IDE hard drive that supports the Identify command should work with the monitor as boot device. The monitor uses the geometry supplied by the Identify command to map blocks to physical cylinder/head/sector addresses. Various Seagate and Maxtor 120-250Mb drives have been tested. 1.1.6. PC-AT Compatible Keyboard The monitor supports PC-AT compatible keyboards. Auto- sensing keyboards may get confused if used, since they may defaults to regular PC-XT mode. The key codes for the XT and AT keyboards are different. Currently, only the AT key codes are supported. The monitor does not drive the status LEDs on the keyboard. 1.2. Software Configuration 1.3. Specifications Processor: MC68030RC16 Clock Speed: 16Mhz Memory: 64Kb EPROM (100ns) 32Kb Static RAM (100ns) 4Mb (1Mbx36) SIMMs (80ns) (parity is not implemented) ISAbus: 8/16bit IO and memory 1Mb address range no DMA capability IRQ2-7 direct IRQ9-15 via MC68901 Keyboard: bidirectional PC-AT keyboard I/F using MC68901 CPUbus: most 68030 processor signals Connections: speaker turbo switch (NMI interrupt) reset switch power LED Keyboard Lock (switches ROM/RAM) turbo LED (run light) January 11, 1994 - 3 - 1.4. Assembly and Installation 1.4.1. Motherboard 1. get part list and select all components. 2. solder all by-pass caps 3. solder all ic sockets 4. solder all ISAbus and CPUbus connectors 5. solder SIMM connector 6. solder misc. components (resistors, diodes, connectors) 7. check board for continuity before applying power 8. with all the chips still removed from their sockets, apply power and check Vcc and Gnd at each socket 9. plug in all the chips and memory 10. plug in a VGA card and keyboard and apply power, if the monitor doesn't come up, proceed to Section "Hardware Debugging" 1.4.2. Installing in Case 1.5. Hardware Debugging Since this is a new design, we don't have any good pro- cedures. Just follow normal debugging procedures with the schematics. Start with checking all the DC levels at the pins of the ICs, then proceed to following the clock to where ever it's suppose to go, check for signal pins that are accidentally shorted to other signals or Vcc and ground, check for bad solder connections and bridges. In the future we will implement some low-level diagnos- tic software that can run in a minimal system and report errors via error codes on the LEDs of the keyboard. 2. Monitor The monitor was written from scratch and is contained in a 64Kb EPROM. After a reset, the monitor copies itself into DRAM starting at location 0xfffe0000, the vector base register is set to this location and it starts autobooting. If no suitable bootstrap is found, or a keystroke interrupts the boot process, the monitor will enter the command loop. The monitor also supports contexts, which are processor states saved by the monitor. When running a high level operating system that is suspended, one of the states is used to hold the state information about the OS to be able to continue it. Other contexts can then be used to debug code without disturbing the OS context. Context 0 is used when booting. January 11, 1994 - 4 - 2.1. Commands The commands in the monitor are very primitive, but support a complete debugging environment complete with vt100 emulator. 2.1.1. ct[state] change context Change the context of the monitor. This will switch the register set. Context 0 is usually used for the host operat- ing system. Context 1 can be used to debug code. 2.1.2. go[address] start executing Start executing at the given address. If no address is specified execution is resumed at the stored pc for the current context. 2.1.3. rd display registers Displays all the registers in the 68010 programmer's model. The stack pointer that is currently used is market with an '*' star. 2.1.4. rm[register] modify registers A hex value will be loaded into the specified registered. The monitor will cycle through all registers starting at the one specified in the command. If no register is specified, it will start at 'D0'. will store the value, "." will exit. 2.1.5. md[address] display memory Displat memory starting at address. If no address is specified, 0 is used the first time and the last accessed memory location is used after that. 2.1.6. mm[address] modify memory A hex value will be loaded into the specified memory location. will store value, "." exit. Also, '=' is used to redisplay the value and '^' to step back one loca- tion. If no address is specified, 0 is used the first time and the last accessed location after that. January 11, 1994 - 5 - 2.1.7. tr[number] trace instructions The specified number of instructions are traced start- ing at the current pc. If a number is not specified a single instruction is traced. 2.1.8. bp[address] set breakpoint Set a breakpoint at specified address. If no address is specified, breakpoint is set at the current pc. Breakpoints are implemented using the 'illegal' instruction. 2.1.9. bc clear breakpoint Clear the breakpoint. 2.1.10. bd display breakpoint List out the address of breakpoint and opcode at that location. 2.1.11. go[address] start execution Start executing at address. If no address is specified, the pc is used. 2.1.12. bo[device] boot from device device specifies the device to boot from. If no device is specified, the monitor will try floppy and hard disk in that order. Currently known devices are: 0 auto boot 1 floppy unit 0 2 IDE unit 0 2.1.13. lo[com] load hex records Download and store a program in Motorola hex format from specified com port. If no com port is specified, com1 is used. 2.1.14. tm[com] transparent mode Enter transparent mode on com port. If no com port is specified, com1 is used. All characters typed on the January 11, 1994 - 6 - keyboard are send to the com port and all characters received are displayed on console. The monitor does under- stand vt100 escape sequences if the console is on VGA. 2.1.15. pr printer toggle Toggles the log printer on and off. If a printer is connected to the parallel port, turning on the printer will log everything that is send to the screen, including output generated by a user program viad the 'putcon' services rou- tine. 2.2. Boot process Upon reset, the monitor will try to autoboot from what- ever device it can find a valid bootstrap on. If a character is typed within a timeout period or no bootstrap is found, the monitor will abort and enter interactive mode. The monitor will try loading the first sector on the device. It will then read the second longword in that sector to determine which sector to read next. The long word after that will contain the number of sectors to read. Finally, after all the sectors are read as specified, the monitor will jump to the first location of the first sector read and start exececuting. This location will normally contain a branch instruction to jump to the proper location in the boot-strap. Offset What 8 ________________________________ 0 branch to code +4 next sector to read +8 how many more blocks 2.3. Trap 15 Monitor Services The monitor also implements services via a trap 15 handler. The following example shows how to call the putcon facility: putchar: move.l (sp)4,d0 trap #15 dc.w 1 rts Currently, the following services are implemented: # Name Description 8 ____________________________________________________________________ 0 halt stop executing and return to monitor 1 putcon print the ASCII character in D0 to the screen January 11, 1994 - 7 - 2 getcon wait for a character and return it's ASCII value in D0 3 constat sample the console, return ASCII or 0 in D0 3. Hardware Description 3.1. Motherboard Logic 3.1.1. Reset A RC circuit followed by a smitt trigger is used to generate the proper reset timing for the processor. The capacitor is charged through a resistor to Vcc. There are several sources, reset switch, "power good" signal, which can cause a reset by discharging the capacitor to Gnd. The sources are wired-or with signal diodes. A Open Collector inverter is used to drive the processor reset pin, which is followed by more inverters that drive the resets to the rest of the board. The processor can reset all devices on the board and the 2 buses with an reset instruction. 3.1.2. Interrupts There are 7 interrupt sources that are encoded with a priority encoder that supplies the processor with the ipl[0-2] signals. The highest priority interrupt (level 7) is tied to the NMI switch with a RC network, much like the reset circuit, to debounce the switch. Level 6 is tied to the MFP, which also handles all the extended ISA bus inter- rupts through its parallel interface. The rest of the inter- rupt levels are connected with inverters directly to the 8bit PCbus interface. All of the interrupts are autovec- tored, by pulling the AVEC signal low. 3.1.3. Timing and Bus timeout generator The 16Mhz master clock is directly tied to the clock pin of the processor, a counter is used to divide the clock to lower frequencies used on the board, a shift register to generate wait-states, and the DRAM sequencer. A gated shift register, which is clocked by the 1Mhz output of the counter is used to generate a bus error in the event that AS is asserted too long (8us). Another counter is used to further divide the 1Mhz clock to a 16us clock which is used for DRAM refresh timing. 3.1.4. DRAM interface The DRAM interface consists of one arbiter and 2 sequencers to generate the proper CAS/RAS timing and MUX control signals for refresh and memory access. The arbiter decides which sequencer gets to proceed between each memory cycle. A flip-flop latches the refresh clock pulse and January 11, 1994 - 8 - causes the arbiter to select the refresh sequencer at the end of the current memory cycle or whenever there are no memory cycles in progress. Once a refresh cycle has started, any memory cycles will stall until refresh is done. Even though with this method refreshes can directly follow memory accesses we didn't implement hidden refreshes, since it would have made the sequencers obscure to follow. The refresh sequencer generates CAS before RAS refresh timing signals, which are send to the DRAM. During a refresh cycle, the write enable to the DRAM is disabled to prevent other bus cycles from writing to DRAM. At the end of the refresh cycle, the sequencer clears the refresh latch. Dur- ing a memory cycle, the memory sequencer asserts RAS, then changes the address MUX select and asserts CAS and STERM. The STERM is OR-ed with the STERM signals from the CPUbus before passing on to the CPU. A PAL selects which CAS is gated to memory depending on the SIZ[0-1] and A[0-1] signals from the processor. During refresh and read cycles, all CAS strobes are asserted. 3.1.5. Decoding The address map is divided into 2 areas with the A31 addess line. A high will select DRAM, and a low will select a 1 of 8 decoder which is selected with A22-20. The 1 of 8 decoder selects EPROM/SRAM/MFP and PCbus IO/Memory and 8/16 bit accesses. Two 1 to 8 MUXes will select the proper signal from the wait-state shift register to generate DSACK[0-1] for each address range. All address mapping can be disabled by a signal from the CPUbus to overlay any address range on the Mother-board as desired. The CPUbus can also supply DSACKs, which are OR-ed with the DSACKs from the rest of the board. 3.1.6. Keyboard I/F and MFP The USART on the MFP is used to interface to an AT key- board. The keyboard data is tied to the RD (receive data) line and the clock to the RC (receive clock). These 2 lines are also tied to 2 of the parallel ports. Since the keyboard signals are open collector, the parallel port lines can drive them low when taken out of tri-state. The parallel port is necessary to monitor the data/clock lines and infor- mation to the keyboard. The remaining parallel IO lines are tied to the IRQ lines on the extended (16 bit) ISA bus con- nector. The output of the d timer is tied to the speaker with a current limiting resistor and a signal diode to reverse protect the driver on the MFP. The 4Mhz clock from is supplied to the MFP for both the system clock and sources for the timers. January 11, 1994 - 9 - 3.2. PCbus 3.2.1. Description 3.2.2. Supported Bus Cycle 3.3. CPUbus 3.3.1. Description 3.3.2. Example Floating Point Interface January 11, 1994 - 10 - Additional Reference Material Motorola 68030 User's Manual Motorola 68901 MFP User's Manual Motorola 68000 Family Programmer's Manual Motorola Memory Data IBM-AT Hardware Reference, Keyboard IBM-AT Hardware Reference, Bus "Interfacing to the IBM Personal Computer", Eggebrecht, SAMS January 11, 1994 - 11 - Physical Memory Map Address Description 8 ____________________________________________ 00000000-000fffff 64Kb EPROM 00100000-001fffff 32Kb SRAM 00200000-002fffff MFP 00300000-003fffff - (causes bus errors) 00400000-004fffff PCbus 16bit IO 00500000-005fffff PCbus 16bit memory 00600000-006fffff PCbus 8bit IO 00700000-007fffff PCbus 8bit memory 00800000-7fffffff repeat above 80000000-803fffff 4Mb DRAM 00400000-ffffffff repeat DRAM 9 January 11, 1994 - 12 - Jumpers and Connections January 11, 1994 - 13 - PCbus pinout January 11, 1994 - 14 - CPUbus pinout January 11, 1994 - 15 - Schematics January 11, 1994 - 16 - Bill of Materials January 11, 1994 - 17 - |Qty |Reference|Part Name |Description +----+---------+--------------+----------------------------- |1 |U1 |MC68030RC16 |2nd Generation 32bit Microprocessor |9 |U2 U15-22|74ALS245 |OCTAL BUS TRANSCEIVER 3 STATE |2 |U3-4 |74ALS164 |8-BIT PARALLEL OUTPUT SERIAL | | | |SHIFT REGISTER |2 |U5-6 |74ALS163A |SYNC 4 BIT BINARY COUNTER W/ | | | |SYNC CLEAR |1 |U7 |OSC.MOD |16Mhz Oscillator Module |2 |U8 U37 |74ALS32 |QUAD 2-INPUT POS-OR GATE |1 |U9 |74ALS05 |HEX INV OC |3 |U10 U38 |74ALS04 |HEX INV |2 |U11-12 |74ALS175 |Quad D Flip-Flop |1 |U13 |74ALS74 |DUAL D-TYPE POSITIVE-EDGE | | | |TRIGGERED FLIP FLOP |2 |U14 U36 |74ALS00 |QUAD 2-INPUT POS-NAND GATE |3 |U24-26 |74ALS158 |QUAD 2-TO-1-LINE DATE | | | |SELECTOR/MULTIPLEXER | | | |OUTPUTS |1 |U23 |SIMM36 | |1 |U27 |PAL16L8 | PROGRAMMABLE ARRAY LOGIC (16v8 programmed as | | | | 16l8) |2 |U28 U39 |74ALS08 |QUAD 2-INPUT POS-AND GATE |1 |U29 |27C512 |64K X 8 BIT CMOS EPROM (120ns) |1 |U30 |62256LP-10 |32K X 8 BIT HIGH SPEED CMOS (100ns) | | | |STATIC RAM |2 |U31-32 |74ALS151 |1-OF-8 DATA |1 |U33 |74ALS138 |3-TO-8 LINE DECODER/DEMUX |1 |U34 |MC68901P8 |Multi Function Peripheral |1 |U35 |74ALS10 |TRIPLE 3-INPUT POS-NAND GATE |1 |U40 |74ALS148 |8-LINE-TO-3-LINE OCTAL | | | |PRIORITY ENCODER |1 |U43 |74ALS21 |DUAL 4-INPUT POS-AND GATE | | | |SELECTOR/MULTIPLEXER |1 |U42 |74ALS14 |HEX SCHMITT-TRIGGER INV |1 |U44 |74ALS20 |DUAL 4-INPUT POS-NAND GATE |46 |C4-49 |CAPMR04,103 |CAP RADIAL BODY: .200 X.100 | | | |CENTERS: .100 |2 |C2-3 |CAPMR04,470 |CAP RADIAL BODY: .200 X.100 | | | |CENTERS: .100 |4 |C50-53 |CAPMR05,106 |CAP RADIAL BODY: .260 X.100 | | | |CENTERS:.200 |2 |C1 C54 |CAPMR05,226 |CAP RADIAL BODY: .260 X.100 | | | |CENTERS:.200 |1 |J1 |ISABUS | 16bit ISAbus connector |1 |J2 |CONDIN5 |CIRCULAR 5-PIN DIN FEMALE PCB |1 |J3 |PCPOWER | Industry Standard Power Connector |1 |J4 |CONSIP4P | GENERIC 4 PIN SIP HEADER | | | |.100 CENTERS |2 |J5 J8 |CONSIP2P | GENERIC 2 PIN SIP HEADER | | | |.100 CENTERS |2 |J6 J9 |CONSIP3P | GENERIC 3 PIN SIP HEADER | | | |.100 CENTERS January 11, 1994 - 18 - |1 |J7 |CONSIP5P | GENERIC 5 PIN SIP HEADER | | | |.100 CENTERS |3 |J10-12 |68030BUS | |4 |D1-4 |DO41 |GENERIC DO41 SIZED DIODE |8 |W4-11 |JMP | |5 |R1 R6 R20|RSIP10P9R+5, |SIP RESISTOR 10 PINS 9 |2 |R3-4 |R1/4W,2.2k |RES BODY:100 CENTERS:500 |2 |R14-15 |R1/4W,150 |RES BODY:100 CENTERS:500 |1 |R13 |R1/4W,33 |RES BODY:100 CENTERS:500 | |R22 R25 |4.7k |RESISTORS TO +5V |3 |R21 |RSIP10P9RG, |SIP RESISTOR 10 PINS 9 | |R23-24 |4.7k |RESISTORS GNDED ------------------------------------------------------------ January 11, 1994