68K/85XX Interface Controller, PAL20X10

logic equations and fuse map


PAL20X10	PAL DESIGN SPECIFICATION
PMSI408	JANE LEE(MMI)/KEN THOMAS(ZILOG)
INTERFACE CONTROLLER FOR 68000 uP TO ZILOG 85XX PERIPHERALS
MMI SUNNYVALE, CALIFORNIA
CLK /CS  NC TEST /AS  RW  FC2  FCl  FCO /RESET  NC  GND
/OC /C3 /C2 /Cl  /C0 /CYC NC  /DTK /RD  /WR    /ACK VCC
C0 :=  /C0*/TEST                                     ;C OUNT/HOLD (LSB)
Cl :=  /RESET* AS* Cl	;HOLD
   :+: /RESET* AS* C0	;DECREMENT
C2 :=  /RESET* AS* C2	;HOLD
   :+: /RESET* AS* C0* Cl	;DECREMENT
C3 :=  /RESET* AS* C3	;HOLD
   :+: /RESET* AS* C0* Cl* C2	; DECREMENT
DTK :=  /RESET * /ACK * CYC * C3 * /C2 * /Cl *  C0 * CS   ; DTACK FOR RD/WR CYCLE
     +  /RESET *  ACK * CYC * C3 * /C2 *  Cl * /C0        ; DTACK FOR INTERRUPT CYCLE
CYC :=  /RESET* AS * /CYC * C0	;START NEW CYCLE
     +  /RESET* AS*   CYC          ;HOLD PROCESS OF CYCLE
    :+: /RESET*       CYC * DTK	;END OF CYCLE
RD :=  /RESET * CYC * /ACK * RW *  C3 * /C2           * CS      ; NORMAL READ OPERATION
    +  /RESET * CYC * /ACK * RW * /C3 *  C2 * Cl * C0 * CS      ; NORMAL READ OPERATION
   :+: /RESET * CYC *  ACR * RW *  C3                           ; READ DURING INTERRUPT
    +   RESET                                            	; RESET
WR :=  /RESET * CYC * /ACK * /RW *  C3 * /C2           * CS     ; WRITE
   +   /RESET * CYC * /ACK * /RW * /C3 *  C2 * Cl * C0 * CS     ; WRITE
   :+:  RESET	                                                ; RESET
ACK :=  /RESET * FC0 * FC1 * FC2 * AS * CYC * /C0	; START OF INTERRUPT ACKNOWLEDGE
+  /RESET * PC0 * FC1 * FC2 * CYC	                ; HOLDS INTERRUPT

FUNCTION TABLE
CLK /OC /RESET /C3 /C2 /Cl /CO TEST /CS 
FC2 FCl FC0 RW /AS /CYC /RD /WR /DTK /ACK
;                           /    //
;C           T/  FFF     /  C//  DA
;L O/  CCCC  SC  CCC  R  A  YRW  TC
;E ER  3210  TS  210  W  S  CDR  KK   CYCLE  COMMENTS

C LL  HHHH  HH  LLL  H  H  HLL  HH     1    INITIALIZATION
C LH  HHHL  LH  LLL  H  H  HHH  HH     2
C LH  HHHH  LH  LLL  H  H  HHH  HH     3
C LH  HHHL  LL  LLL  H  H  HHH  HH     4
C LH  HHLH  LL  LLL  H  L  LHH  HH     5    BEGINNING OF WAIT FOR READ CYCLE
C LH  HHLL  LL  LLL  H  L  LHH  HH     6
C LH  HLHH  LL  LLL  H  L  LHH  HH     7
C LH  HLHL  LL  LLL  H  L  LHH  HH     8
C LH  HLLH  LL  LLL  H  L  LHH  HH     9
C LH  HLLL  LL  LLL  H  L  LHH  HH    10
C LH  LHHH  LL  LLL  H  L  LLH  HH    11    /RD GOES ACTIVE
C LH  LHHL  LL  LLL  H  L  LLH  HH    12
C LH  LHLH  LL  LLL  H  L  LLH  LH    13    ACKNOWLEDGE END OF DATA TRANSFER
C LH  LHLL  LL  LLL  H  L  HLH  HH    14    END OF READ CYCLE
C LH  HHHH  LH  LLL  H  H  HHH  HH    15    INITIALIZATION
C LH  HHHL  LH  LLL  H  H  HHH  HH    16
C LH  HHLH  LL  LLL  L  L  LHH  HH    17    BEGINNING OF WAIT FOR WRITE CYCLE
C LH  HHLL  LL  LLL  L  L  LHH  HH    18
C LH  HLHH  LL  LLL  L  L  LHH  HH    19
c LH  HLHL  LL  LLL  L  L  LHH  HH    20
C LH  HLLH  LL  LLL  L  L  LHH  HH    21
C LH  HLLL  LL  LLL  L  L  LHH  HH    22
C LH  LHHH  LL  LLL  L  L  LHL  HH    23    /WR GOES ACTIVE
C LH  LHHL  LL  LLL  L  L  LHL  HH    24
C LH  LHLH  LL  LLL  L  L  LHL  LH    25    ACKNOWLEDGE END OF DATA TRANSFER
C LH  LHLL  LL  LLL  L  L  HHL  HH    26    END OF WRITE CYLE
C LH  HHHH  LH  LLL  H  H  HHH  HH    27    INITIALIZATION
C LH  HHHL  LH  LLL  H  H  HHH  HH    28
C LH  HHLH  LH  HHH  H  L  LHH  HH    29    INTERRUPT CYCLE (WAITS RD SIGNAL)
C LH  HHLL  LH  HHH  H  L  LHH  HL    30
C LH  HLHH  LH  HHH  H  L  LHH  HL    31
C LH  HLHL  LH  HHH  H  L  LHH  HL    32
C LH  HLLH  LH  HHH  H  I  LHH  HL    33
C LH  HLLL  LH  HHH  H  L  LHH  HL    34
C LH  LHHH  LH  HHH  H  L  LHH  HL    35
C LH  LHHL  LH  HHH  H  L  LLH  HL    36    /RD GOES ACTIVE
C LH  LHLH  LH  HHH  H  L  LLH  HL    37
C LH  LHLL  LH  HHH  H  L  LLH  LL    38
C LH  LLHH  LH  HHH  H  L  HLH  HL    39
C LH  HHHL  LH  LLL  H  H  HHH  HH    40    END OF CYCLE

Description

The PAL provides a single chip interface controller for interfacing Motorola's 8 MHz 6800 microprocessor to Zilog's 4 MHz z85xx peripheral. The interface controller generates all the required control signals, if which four /RD, /MR, PCLK (=/C0), and /ACK go to the z85xx and /DTK goes to the 68000.

In addition to generating control signals, the interface controller has the capability of controlling three types of bus cycles; read, write, and interrupt acknowledge.

Timing for processing of data transfer is controlled with an internal down counter. A counter decoder controls timing of /DTK (data transfer acknowledge) to the 68000 to inform a complete data transfer cycle.

These operations are exercised in the function table and summarized in the operation table:

/C  /// FFF  //DCA
OL/ ACR CCC  WRTYC
CKR SSW 210  RDKCK	OPERATION

Hxx XXX XXX  ZZZZZ	HI-Z
LCL XXX XXX  LLHHH      INITIALIZATION
LCH LLH LLL  HLHLH	READ
LCH LLL LLL  LHHLH	WRITE
LCH LHH HHH  HLHLL	READ DURING INTERRUPT

Functional description

The pal generates five control signals at which /RD, /MR, PCLK (=/C0), and /ACK to the z85xx and /DTK goes to the 68000. /RD, /MR, and /ACK are three types of z85xx cycles, which are controlled by the pal:

/RD - read cycle
/WR - write cycle
/ACK - interrupt acknowledge cycle

/C0, /C1, /C2, and /C3 are part of a 4-bit synchronous down counter where /C3 is the MSB and /C0 is the LSB. /C0 is simply a divide by 2 of the 68000 clock used by the peripheral for PCLK. The other three signals, C1, C2, C3 with /CYC are used internal to the pal for generating the above control signals.

The counter toggles between 14 and 15 until /CYC (=cycle) goes active low and then will begin counting down. The counter will continue counting down until /as goes inactive high, signalling the end of cycle. At this time the counter will go back to toggling between count 14 and 15. Refer to the function table.

The control signals, /RD, /WR, /ACK, and /DTK are generated through the pal and qualified with the counter to generate edges that meet time restraints.