Project Information    c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 03/15/2002 00:32:11

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


Title: Apple II  IDE/CompactFlash Interface
Company: R&D Automation
Designer: Richard Dreher & Chris Schumann
Rev: A
Date: 12:27a  3-15-2002


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

appleideinterface
      EPM7064SLC44-10      12       13       0      14      11          21 %

User Pins:                 12       13       0  



Project Information    c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal '7Mclk' chosen for auto global Clock


Project Information    c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

appleideinterface@21                 A0
appleideinterface@20                 A1
appleideinterface@19                 A2
appleideinterface@18                 A3
appleideinterface@17                 A8
appleideinterface@16                 A9
appleideinterface@14                 A10
appleideinterface@24                 CS_MASK
appleideinterface@40                 -CS0
appleideinterface@41                 -CS1
appleideinterface@27                 C800_ACT
appleideinterface@25                 DBUS245
appleideinterface@6                 -DevSelect
appleideinterface@29                 -EPROM_EN
appleideinterface@39                 -IORD
appleideinterface@4                 -I/OSelect
appleideinterface@5                 -I/OStrobe
appleideinterface@37                 -IOWR
appleideinterface@26                 NOT_R/W
appleideinterface@33                 R_ATA
appleideinterface@31                 -R_HOST
appleideinterface@12                 R/W
appleideinterface@36                 -W_ATA
appleideinterface@34                 W_HOST
appleideinterface@43                 7Mclk


Project Information    c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt

** FILE HIERARCHY **



|appleidelogic:141|
|appleidelogic:141|nandltch:52|
|appleidelogic:141|nandltch:56|


Device-Specific Information:c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt
appleideinterface

***** Logic for device 'appleideinterface' compiled without errors.




Device: EPM7064SLC44-10

Device Options:
    Turbo Bit                                    = OFF
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff

                -  -  -                          
                D  I  I                          
                e  /  /                          
                v  O  O                          
                S  S  S                          
                e  t  e              7           
                l  r  l              M     -  -  
                e  o  e  V  G  G  G  c  G  C  C  
                c  b  c  C  N  N  N  l  N  S  S  
                t  e  t  C  D  D  D  k  D  1  0  
              -----------------------------------_ 
            /   6  5  4  3  2  1 44 43 42 41 40   | 
      #TDI |  7                                39 | -IORD 
  RESERVED |  8                                38 | #TDO 
  RESERVED |  9                                37 | -IOWR 
       GND | 10                                36 | -W_ATA 
  RESERVED | 11                                35 | VCC 
       R/W | 12        EPM7064SLC44-10         34 | W_HOST 
      #TMS | 13                                33 | R_ATA 
       A10 | 14                                32 | #TCK 
       VCC | 15                                31 | -R_HOST 
        A9 | 16                                30 | GND 
        A8 | 17                                29 | -EPROM_EN 
           |_  18 19 20 21 22 23 24 25 26 27 28  _| 
             ------------------------------------ 
                A  A  A  A  G  V  C  D  N  C  R  
                3  2  1  0  N  C  S  B  O  8  E  
                            D  C  _  U  T  0  S  
                                  M  S  _  0  E  
                                  A  2  R  _  R  
                                  S  4  /  A  V  
                                  K  5  W  C  E  
                                           T  D  
                                                 
                                                 


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt
appleideinterface

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     1/16(  6%)   5/ 8( 62%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)   8/ 8(100%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48     6/16( 37%)   7/ 8( 87%)   7/16( 43%)  11/36( 30%) 
D:    LC49 - LC64     7/16( 43%)   8/ 8(100%)   4/16( 25%)   7/36( 19%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            28/32     ( 87%)
Total logic cells used:                         14/64     ( 21%)
Total shareable expanders used:                 11/64     ( 17%)
Total Turbo logic cells used:                    0/64     (  0%)
Total shareable expanders not available (n/a):   0/64     (  0%)
Average fan-in:                                  5.14
Total fan-in:                                    72

Total input pins required:                      12
Total fast input logic cells required:           1
Total output pins required:                     13
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     14
Total flipflops required:                        1
Total product terms required:                   37
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           7

Synthesized logic cells:                         0/  64   (  0%)



Device-Specific Information:c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt
appleideinterface

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  21   (17)  (B)      INPUT               0      0   0    0    0    7    0  A0
  20   (19)  (B)      INPUT               0      0   0    0    0    9    0  A1
  19   (20)  (B)      INPUT               0      0   0    0    0    9    0  A2
  18   (21)  (B)      INPUT               0      0   0    0    0    9    0  A3
  17   (24)  (B)      INPUT               0      0   0    0    0    3    0  A8
  16   (25)  (B)      INPUT               0      0   0    0    0    3    0  A9
  14   (30)  (B)      INPUT               0      0   0    0    0    3    0  A10
   6     11    A         FF   +           0      0   0    0    0    2    0  -DevSelect
   4   (16)  (A)      INPUT               0      0   0    0    0    3    0  -I/OSelect
   5   (14)  (A)      INPUT               0      0   0    0    0    3    0  -I/OStrobe
  12    (1)  (A)      INPUT               0      0   0    0    0    9    0  R/W
  43      -   -       INPUT  G            0      0   0    0    0    0    0  7Mclk


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt
appleideinterface

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  24     33    C     OUTPUT       /       4      4   0    5    0    0    0  CS_MASK
  40     62    D     OUTPUT       /       4      4   0    6    0    0    0  -CS0
  41     64    D     OUTPUT       /       4      4   0    6    0    0    0  -CS1
  27     37    C     OUTPUT       /       3      3   0    5    0    0    0  C800_ACT
  25     35    C     OUTPUT       /       3      3   0    6    0    0    0  DBUS245
  29     41    C     OUTPUT       /       3      3   0    5    0    0    0  -EPROM_EN
  39     57    D     OUTPUT       /       0      0   0    6    1    0    0  -IORD
  37     53    D     OUTPUT       /       0      0   0    6    1    0    0  -IOWR
  26     36    C     OUTPUT       /       0      0   0    1    0    0    0  NOT_R/W
  33     49    D     OUTPUT       /       0      0   0    5    0    0    0  R_ATA
  31     46    C     OUTPUT       /       0      0   0    6    0    0    0  -R_HOST
  36     52    D     OUTPUT       /       0      0   0    5    0    0    0  -W_ATA
  34     51    D     OUTPUT       /       0      0   0    6    0    0    0  W_HOST


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt
appleideinterface

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

           Logic cells placed in LAB 'A'
        +- LC11 -DevSelect
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'A'
LC      | | A B C D |     Logic cells that feed LAB 'A':

Pin
43   -> - | - - - - | <-- 7Mclk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt
appleideinterface

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                     Logic cells placed in LAB 'C'
        +----------- LC33 CS_MASK
        | +--------- LC37 C800_ACT
        | | +------- LC35 DBUS245
        | | | +----- LC41 -EPROM_EN
        | | | | +--- LC36 NOT_R/W
        | | | | | +- LC46 -R_HOST
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'C'
LC      | | | | | | | A B C D |     Logic cells that feed LAB 'C':

Pin
21   -> * - - - - * | - - * * | <-- A0
20   -> * - - - - * | - - * * | <-- A1
19   -> * - - - - * | - - * * | <-- A2
18   -> * - - - - * | - - * * | <-- A3
17   -> - * * * - - | - - * - | <-- A8
16   -> - * * * - - | - - * - | <-- A9
14   -> - * * * - - | - - * - | <-- A10
6    -> * - * - - * | - - * * | <-- -DevSelect
4    -> - * * * - - | - - * - | <-- -I/OSelect
5    -> - * * * - - | - - * - | <-- -I/OStrobe
12   -> - - - - * * | - - * * | <-- R/W
43   -> - - - - - - | - - - - | <-- 7Mclk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt
appleideinterface

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                       Logic cells placed in LAB 'D'
        +------------- LC62 -CS0
        | +----------- LC64 -CS1
        | | +--------- LC57 -IORD
        | | | +------- LC53 -IOWR
        | | | | +----- LC49 R_ATA
        | | | | | +--- LC52 -W_ATA
        | | | | | | +- LC51 W_HOST
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | A B C D |     Logic cells that feed LAB 'D':

Pin
21   -> * * * * - - * | - - * * | <-- A0
20   -> * * * * * * * | - - * * | <-- A1
19   -> * * * * * * * | - - * * | <-- A2
18   -> * * * * * * * | - - * * | <-- A3
6    -> * * * * * * * | - - * * | <-- -DevSelect
12   -> * * * * * * * | - - * * | <-- R/W
43   -> - - - - - - - | - - - - | <-- 7Mclk
LC11 -> - - * * - - - | - - - * | <-- -DevSelect


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt
appleideinterface

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A8       : INPUT;
A9       : INPUT;
A10      : INPUT;
R/W      : INPUT;
7Mclk    : INPUT;
-I/OSelect : INPUT;
-I/OStrobe : INPUT;

-- Node name is 'CS_MASK' 
-- Equation name is 'CS_MASK', location is LC033, type is output.
 CS_MASK = LCELL( _EQ001 $  GND);
  _EQ001 =  _X001;
  _X001  = EXP( _X002 &  _X003);
  _X002  = EXP( _X001 &  _X004);
  _X003  = EXP( A0 & !A1 & !A2 & !A3 & !-DevSelect);
  _X004  = EXP(!A0 &  A1 & !A2 & !A3 & !-DevSelect);

-- Node name is 'C800_ACT' 
-- Equation name is 'C800_ACT', location is LC037, type is output.
 C800_ACT = LCELL( _EQ002 $  GND);
  _EQ002 =  _X005 &  _X006;
  _X005  = EXP( -I/OSelect &  _X007);
  _X006  = EXP( A8 &  A9 &  A10 & !-I/OStrobe);
  _X007  = EXP( _X005 &  _X006);

-- Node name is 'DBUS245' 
-- Equation name is 'DBUS245', location is LC035, type is output.
 DBUS245 = LCELL( _EQ003 $  GND);
  _EQ003 =  -DevSelect &  -I/OSelect &  _X007
         #  -DevSelect &  -I/OSelect &  -I/OStrobe;
  _X007  = EXP( _X005 &  _X006);
  _X005  = EXP( -I/OSelect &  _X007);
  _X006  = EXP( A8 &  A9 &  A10 & !-I/OStrobe);

-- Node name is 'NOT_R/W' 
-- Equation name is 'NOT_R/W', location is LC036, type is output.
 NOT_R/W = LCELL(!R/W $  GND);

-- Node name is 'R_ATA' 
-- Equation name is 'R_ATA', location is LC049, type is output.
 R_ATA   = LCELL( _EQ004 $  GND);
  _EQ004 =  A1 &  A2 & !-DevSelect &  R/W
         #  A3 & !-DevSelect &  R/W;

-- Node name is 'W_HOST' 
-- Equation name is 'W_HOST', location is LC051, type is output.
 W_HOST  = LCELL( _EQ005 $  GND);
  _EQ005 = !A0 & !A1 & !A2 & !A3 & !-DevSelect & !R/W;

-- Node name is '-CS0' 
-- Equation name is '-CS0', location is LC062, type is output.
 -CS0    = LCELL( _EQ006 $  VCC);
  _EQ006 =  A3 & !-DevSelect &  _X002 &  _X003
         #  A3 & !-DevSelect & !R/W;
  _X002  = EXP( _X001 &  _X004);
  _X003  = EXP( A0 & !A1 & !A2 & !A3 & !-DevSelect);
  _X001  = EXP( _X002 &  _X003);
  _X004  = EXP(!A0 &  A1 & !A2 & !A3 & !-DevSelect);

-- Node name is '-CS1' 
-- Equation name is '-CS1', location is LC064, type is output.
 -CS1    = LCELL( _EQ007 $  VCC);
  _EQ007 =  A1 &  A2 & !A3 & !-DevSelect &  _X002 &  _X003
         #  A1 &  A2 & !A3 & !-DevSelect & !R/W;
  _X002  = EXP( _X001 &  _X004);
  _X003  = EXP( A0 & !A1 & !A2 & !A3 & !-DevSelect);
  _X001  = EXP( _X002 &  _X003);
  _X004  = EXP(!A0 &  A1 & !A2 & !A3 & !-DevSelect);

-- Node name is '|appleidelogic:141|DelayDSEL' from file "appleidelogic.tdf" line 64, column 14
-- Equation name is '_IOC_6', type is buried 
-DevSelect : INPUT;
_IOC_6   = DFFE(-DevSelect, GLOBAL( 7Mclk),  VCC,  VCC,  VCC);

-- Node name is '-EPROM_EN' 
-- Equation name is '-EPROM_EN', location is LC041, type is output.
 -EPROM_EN = LCELL( _EQ008 $  -I/OSelect);
  _EQ008 = !-I/OStrobe &  _X005 &  _X006;
  _X005  = EXP( -I/OSelect &  _X007);
  _X006  = EXP( A8 &  A9 &  A10 & !-I/OStrobe);
  _X007  = EXP( _X005 &  _X006);

-- Node name is '-IORD' 
-- Equation name is '-IORD', location is LC057, type is output.
 -IORD   = LCELL( _EQ009 $  GND);
  _EQ009 = !A0 & !A1 & !A2 & !A3
         #  _IOC_6
         #  -DevSelect
         # !R/W;

-- Node name is '-IOWR' 
-- Equation name is '-IOWR', location is LC053, type is output.
 -IOWR   = LCELL( _EQ010 $  GND);
  _EQ010 = !A0 & !A1 & !A2 & !A3
         #  R/W
         #  _IOC_6
         #  -DevSelect;

-- Node name is '-R_HOST' 
-- Equation name is '-R_HOST', location is LC046, type is output.
 -R_HOST = LCELL( _EQ011 $  VCC);
  _EQ011 = !A0 & !A1 & !A2 & !A3 & !-DevSelect &  R/W;

-- Node name is '-W_ATA' 
-- Equation name is '-W_ATA', location is LC052, type is output.
 -W_ATA  = LCELL( _EQ012 $  VCC);
  _EQ012 =  A1 &  A2 & !-DevSelect & !R/W
         #  A3 & !-DevSelect & !R/W;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs C, D
--    _X002 occurs in LABs C, D
--    _X003 occurs in LABs C, D
--    _X004 occurs in LABs C, D




Project Information    c:\progs\cffa\pldlogic\version1.2\appleideinterface.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = part
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = on
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = off
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = on

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = on
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:04
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,124K
