Path: ns-mx!uunet!zaphod.mps.ohio-state.edu!mips!ptimtc!nntp-server.caltech.edu!toddpw
From: toddpw@cco.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: SSC questions
Message-ID: <1991Aug27.220051.4663@cco.caltech.edu>
Date: 27 Aug 91 22:00:51 GMT
References: <17340@mentor.cc.purdue.edu>
Distribution: usa
Organization: California Institute of Technology, Pasadena
Lines: 44

ericm@sage.cc.purdue.edu (Eric Mulholland) writes:

>  3.  Would someone help me with bits 2-4 in the command register,
>      $C08A+$s0.  This is the only thing I'm not clear about.  If I
>      understand things right, the SSC can(?) use interupts for
>      transmitting?  I know it can (and should) use them for recieves.

You can enable interrupts for receiving and/or transmitting. Most programs
only use receive interrupts because the behavior is simple: if recieve
interrupts are enabled then the 6551 will interrupt every time a character
is completely recieved (including error conditions). When this happens
the top bit of the status register is set and the other bits reflect the
status of the character just received. Reading the status register clears
the top bit and resets the interrupt ALWAYS!! Most programs poll transmission
and if the interrupt occurs in the middle of the instruction that checks
the status register to see if it is full, then the interrupt will be lost
and the transmit routine has to deal with it (or not, and lose a character).

Transmit interrupts work differently. I highly recommend the Rockwell data
sheet for more info. When you enable transmit interrupts, nothing happens
until you actually send a character. From that point on, every time it
becomes safe to write a character into the transmit data register the
6551 will interrupt and the top bit of the status register will be set.
(The transmit buffer empty bit in the status register will also be set, of
course.) This means your interrupt routine has to deal with both receiving
and transmitting, possibly in the same interrupt, because the 6551 only
remembers that an interrupt is still pending, not how many there are.

But wait, there's more: if you _don't_ refill the transmit data register
(when there's nothing to transmit) the 6551 will continue to issue transmit
interrupts at the character transmission rate. This means your interrupt
handler, once transmit interrupts have been "kicked in" by the first
transmitted character, will automatically be polled at the character rate
for characters to send. Also note that when you load the transmit data
register and the 6551 isn't currently sending anything, that data almost
immediately gets put in the transmitter and it pulls a transmit interrupt
right away -- the whole process starts again.

The 6551 is about the simplest darn hardware that can maintain continuous
reception _and_ transmission, given adequate interrupt response. It's
way elegant; I like that.

Todd Whitesel
toddpw @ tybalt.caltech.edu