Fujitsu's advanced F²MC8L CPU core consists of seven 16 bit registers plus a maximum of 32 register banks, each consisting of eight 8 bit registers.
The register banks can be used for a high speed context switch after an interrupt.
CPU Core Features:
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8 bit CPU Core
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Highly efficient Instruction Set
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Two 16 bit Accumulators with A-T architecture
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Data operation: 1/8/16 bit
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Enhanced bit manipulation: Clear, Set and Test bit
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64KB Program/Data memory address space
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Multiply and Divide operations
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F²MC Power saving Modes:
| GEAR | Dynamic selection of CPU cycle time in four ratios |
| SUB RUN* | Switch to run from sub-clock and turn off main oscillator |
| SLEEP | Peripheral functions are running, CPU Core is in power down |
| CLOCK* | Only the low speed clock and prescaler are running |
| STOP | Chip is in complete power down |
*where 2nd low speed clock available
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