Duty Cycle Measurement
on DLCK pin 		Related Documentation
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DESCRIPTION

While connecting a display to a graphic controller, in some cases the duty cycle of the provided display clock (DCLK) is very important because some displays need an exact 50 to 50 duty cycle. At the CREMSON-series the display clock depends on the settings for your display. Calculating the prescaler-value with the 200.45 MHz internal display unit main clock you will get the value of DCLK. However, only in some cases the duty cycle of the DCLK is 50% high and 50% low.

DOCUMENTATION

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Application Note Duty Cycle Measurement on DLCK pin V1-00
5 pages, 39 KB


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