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General-purpose register architecture
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Linear space for 32-bit (4 Gbyte) addressing
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16-bit fixed instruction length (excluding immediate data, coprocessor instructions)
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5-stage pipeline configuration for basic instructions, one-instruction one-cycle execution
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32-bit by 32-bit computation enables completion of multiplication instructions within five cycles
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Stepwise division instructions enable 32-bit/ 32-bit division
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Direct addressing instructions for peripheral circuit access
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Coprocessor instructions for direct designation of peripheral accelerator
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High speed interrupt processing complete within 6 cycles
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