 |
Clock
|
|
Internal oscillator circuit and PLL clock multiplication circuit
|
|
Oscillation clock
|
Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the oscillation
|
|
Clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation
|
|
Clock multiplied by one to four (4 MHz to 16 MHz for a 4 MHz base oscillation) .
|
|
Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = x 4, VCC = 5.0 V)
|
|
|
Maximum CPU memory space : 16 MB
|
24-bit addressing
|
|
Bank addressing
|
|
|
Instruction set
|
Bit, byte, word, and long word data types
|
|
23 different addressing modes
|
|
Enhanced calculation precision using a 32-bit accumulator
|
|
Enhanced signed multiplication and division instructions and RETI instruction
|
|
|
Instruction set designed for high level language (C) and multi-tasking
|
Uses a system stack pointer
|
|
Symmetric instruction set and barrel shift instructions
|
|
|
Program patch function (2 address pointers) .
|
|
4-byte instruction queue
|
|
Interrupt function
|
Priority levels are programmable
|
|
32 interrupts
|
|
|
Data transfer function
|
Extended intelligent I/O service function : Up to 16 channels
|
|
|
Low-power consumption modes
|
Sleep mode (CPU operating clock stops.)
|
|
Timebase timer mode (Only oscillation clock and timebase timer continue to operate.)
|
|
Stop mode (Oscillation clock stops.)
|
|
CPU intermittent operation mode (The CPU operates intermittently at the specified interval.)
|
|
|
Package
|
LQFP-64P (FPT-64P-M09 : 0.65 mm pin pitch)
|
|
QFP-64P (FPT-64P-M06 : 1.00 mm pin pitch)
|
|
SH-DIP (DIP-64P-M01 : 1.778 mm pin pitch)
|
|
|
Process : CMOS technology
|
