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F²MC-8L family CPU core
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Dual-clock control system
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Maximum memory size: 16-Kbyte ROM, 512-byte RAM (max.)
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Minimum execution time: 0.95µs/4.2 MHz
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I/O ports: max. 54 channels
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21-bit time-base counter
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8/16-bit timer/counter: 2 or 1 channels
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8-bit serial I/O: 1 channel
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External interrupts (wake-up function): Four channels with edge selection plus eight level-interrupt channels
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8-bit A/D converter: 8 channels
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8-bit PWM timers: 2 channels
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Watch prescaler (15 bits)
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LCD controller/driver: 24 segments * 4 commons (max. 96 pixels)
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LCD driving reference voltage generator and booster (option)
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Remote control transmission output
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Buzzer output
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Power-on reset function (option)
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Low-power consumption modes (stop, sleep, and watch mode)
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CMOS technology
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