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Various package options
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Three types of QFP packages ( 1-mm, 0.65-mm, or 0.5-mm lead pitch)
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SH-DIP package
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High-speed operating capability at low voltage
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Minimum execution time: 0.32µs/12.5MHz
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F²MC-8L family CPU core
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Instruction set optimized for controllers
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Multiplication and division instructions
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16-bit arithmetic operations
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Test and branch instructions
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Bit manipulation instructions, etc.
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Dual-clock control system
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Main clock: 12.5MHz
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Subclock: 32.768 kHz
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Five types of timers
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8-bit PWM timer: 2 channels timers (also usable as a interval timer)
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16-bit timer/counter
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21-bit time-base timer
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8 bit PWC timer operation
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Watch prescaler (17 bits)
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UART
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CLK-synchronous/CLK-asynchronous data transfer capable
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Serial interface: Switchable transfer direction allows communication with various equipment.
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10-bit A/D converter (8 channels): Activation by timebase timer , external trigger or software.
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Two Type of progammable Pulse Generator (PPG):
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6-bit PPG with program-selectable pulse width and period.
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12-bit PPG (2 channels) with program-selectable pulse width and period.
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I²C interface circuit
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External interrupt 1: Four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function).
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External interrupt 2: Eight channels are independent and capable of wake-up from low-power consumption modes (with a low level detection function).
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Low-power consumption modes
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Stop mode (Oscillation stops to minimize the current consumption.)
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Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
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Subclock mode
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Watch mode
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Watch dog timer reset
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I/O ports: max. 53 channels
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