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F²MC-8L family CPU core
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Instruction set optimized for controllers
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Multiplication and division instructions
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16-bit arithmetic operations
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Test and branch instructions
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Bit manipulation instructions, etc.
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High-speed processing at low voltage
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Minimum execution time: 0.4µs@3.5 V, 0.8µs@2.7 V, 2.0µs@2.2 V
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I/O ports: max. 69 channels
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Timers: 9 channels (MB89675AR/677AR/P677A/PV670A: 12 channels)
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8-bit PWM timer: 3 channels (MB89675AR/677AR/P677A/PV670A: 6 channels) (also usable as a reload timer or 8-bit PWM timer)
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16-bit timer/counter
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21-bit timebase timer
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8/16-bit timer (8 bits * 2 channels or 16 bits)
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8/16-bit up/down counter/timer (8 bits * 2 channels or 16 bits)
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2-channel serial interfaces:
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8-bit synchronized serial: 1 channel (Switchable transfer direction allows communication with various equipment.)
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UART: 1 channel (internal full-duplex double buffer)
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External interrupts: Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function).
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Buzzer output
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10-bit A/D converter: Input: 8 channels
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Low-power consumption modes
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Stop mode (Oscillation stops to minimize the current consumption.)
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Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
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Bus interface function: Including hold and ready functions
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