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Minimum instruction execution time: 0.8µs at 5 MHz
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F²MC-8L family CPU core
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Instruction system most suited to controllers
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Multiplication and division instructions
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16-bit arithmetic operation
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Instruction test and branch instruction
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Bit manipulation instruction, etc.
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LCD controller/driver
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Maximum 42 segment outputs * 4 common outputs
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Build-in LCD driver split resistor
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Three-channel timer unit
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8-bit PWM timer: (usable as both reload timer and PWM timer)
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8-bit pulse width counter timer: (usable as both reload timer)
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20-bit timebased counter
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Two serial interfaces
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8-bit synchronous serial interface
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UART (5, 7, and 8-bit transfers possible)
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External-interrupt input: 2 channels
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2 channels can be used to clear the low-power consumption modes
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An edge detection function is provided for each channel
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Low-power consumption modes
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Stop mode (Oscillation stops to minimize the current consumption)
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Sleep mode (CPU stops to reduce current consumption to about 30%)
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Package: QFP-64 (0.65mm pitch)
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