MB90460 Series

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DESCRIPTION

The MB90460 series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F²MC(*) family, the instruction set for the F²MC-16LX CPU core of the MB90460 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90460 has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90460 series include: an 8/10-bit A/D converter, UARTs (SCI) 0 to 1, 16-bit PPG timer, multi-functional timer (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 and 5, 16-bit PPG timer, waveform generator), multi-pulse generator (16-bit PPG timer, 16-bit reload timer, waveform sequencer), PWC 0 to 1, 16-bit reload timer and DTP/external interrupt. Notes: *: F²MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

FEATURES

Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4 Maximum memory space 16 Mbyte Linear/bank access Instruction set optimized for controller applications Supported data types: bit, byte, word, and long-word types Standard addressing modes: 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division and extended RETI instructions Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions Program patch function (for two address pointers) Enhanced execution speed : 4 byte instruction queue Enhanced interrupt function Up to eight priority levels programmable External interrupt inputs: 8 lines Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs: 8 lines Internal ROM FLASH: 64 Kbyte (with flash security) MASKROM: 64 Kbyte Internal RAM EVA: 8 Kbyte FLASH: 2 Kbyte MASKROM: 2 Kbyte General-purpose ports Up to 51 channels (Input pull-up resistor settable for: 16 channels) A/D Converter (RC) : 8 ch 8/10-bit resolution selectable Conversion time: 6.13 µs (Min.) , 16 MHz operation UART : 2 channels 16 bit PPG : 3 channels Mode switching function provided (PWM mode or one-shot mode) Can be worked with multi-functional timer, multi-pulse generator or individually 16 bit reload timer: 2 channels Can be worked with multi-pulse generator or individually 16-bit PWC timer: 2 channels Multi-functional timer Input capture : 4 channels Output compare with selectable buffer : 6 channels Free run timer with up or up/down mode selection and selectable buffer: 1 channel 16-bit PPG : 1 channel Waveform generator : (16-bit timer: 3 channels, 3-phase waveform or dead time) Multi-pulse generator 16-bit PPG : 1 channel 16-bit reload timer : 1 channel Waveform sequencer : (16-bit timer with buffer and compare clear function) Time-base counter/watchdog timer: 18-bit Low-power consumption mode : Sleep mode Stop mode CPU intermittent operation mode Package: QFP-64 (FPT-64P-M09 : 0.65 mm pitch) QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch) CMOS technology

DOCUMENTATION

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Datasheet DRAFTV1-00 112 pages, 2009 KB Hardware Manual DRAFTV2-10 766 pages, 9623 KB PFM package 0.65mm QFP 1 page, 49 KB PF package 1mm QFP 1 page, 80 KB P-SH package 1.778mm DIP: MB89850 1 page, 64 KB Click here to look for more recent documents!