MB90550A Series
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DESCRIPTION

The MB90550A series is a line of general-purpose, high-performance, 16-bit microcontrollers designed for applications which require high-speed real-time processing, such as industrial machines, OA equipment, and process control systems. While inheriting the AT architecture of the F²MC-8 family(F²MC stands for FUJITSU Flexible Microcontroller), the instruction set for the MB90550A series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90550A has an on-chip 32-bit accumulator which enables processing of long-word data.

FEATURES


Minimum instruction execution time: 62.5 ns (at oscillation of 4MHz, *four times the PLL clock)

Maximum memory space: 16 Mbytes

Instruction system optimized for controller applications

Supported data types (bit, byte, word, long-word)

Typical addressing mode: 23 types

Enhanced precision calculation realized by the 32-bit accumulator

Enhanced signed multiplication/division instructions and RETI instruction functions

Instruction set designed for high-level language (C) and multi-task operations

Adoption of system stack pointer

Symmetrical instruction set and barrel shift instructions

Address match detection function integrated (for two address pointers)

Faster execution speed : 4-byte queue

Powerful interrupt functions (Eight priority levels programmable)

External interrupt inputs : 8 channels

Data transfer functions (Intelligent I/O service) : Up to 16 channels

DTP request inputs : 8 channels

Embedded ROM size (EPROM, Flash : 128 Kbytes)

Mask ROM : 64 Kbytes/128 Kbytes

Embedded RAM size (EPROM, Flash : 4 Kbytes)

Mask ROM : 2 Kbytes/4 Kbytes

General-purpose ports :Up to 83 channels

(Input pull-up resistor settable for : 16 channels

Open drain settable for : 8 channels

I/O open drains : 6 channels)

A/D converter (RC successive approximation type): 8 channels

(Resolution: 8 or 10 bits selectable; Conversion time of 26.3µs minimum)

UART : 1 channel

Extended I/O serial interface : 2 channels

I²C interface : 2 channels

(Two channels, including one switchable between terminal input and output)

16-bit reload timer : 2 channels

8/16-bit PPG timer : 3 channels

(8 bits x 2 channels; 16 bits x 1 channel: Mode switching function provided)

16-bit I/O timer

(Input capture x 4 channels, output compare x 4 channels, free run timer x1 channel

Clock monitor function integrated (Delivering the oscillation clock divided by 21 to 28)

Timebase timer/watchdog timer : 18 bit

Low power consumption modes (sleep, stop, hardware standby, and CPU intermittent operation modes)

Package : QFP-100, LQFP-100

CMOS technology


DOCUMENTATION

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Datasheet Datasheet V2-00
58 pages, 696 KB
Hardware Manual Hardware Manual V3-00
480 pages, 8936 KB
Hardware Manual Hardware Manual Corrections X1-00
2 pages, 6 KB
Package Drawing PF package 0.65mm QFP
1 page, 109 KB
Package Drawing PFV package 0.5mm LQFP
1 page, 104 KB


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