 |
Minimum instruction execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication), maximum multiplier = 4
|
|
Instruction set optimized for controller applications
|
Upward object code compatibility with F²MC-16 (H)
|
|
Wide range of data types (bit/byte/word/long word)
|
|
Improved instruction cycles provide increased speed
|
|
Additional addressing modes: 23 modes
|
|
High code efficiency
|
|
Access methods (bank access/linear pointer)
|
|
Enhanced multiplication and division instructions (signed instructions added)
|
|
High precision operations are enhanced by use of a 32-bit accumulator
|
|
Extended intelligent I/O service (access area extended to 64 Kbytes)
|
|
Maximum memory space: 16 Mbytes
|
|
|
Enhanced high level language (C)/multitasking support instructions
|
Use of a system stack pointer
|
|
Enhanced pointer indirect instructions
|
|
Barrel shift instructions
|
|
Stack check function
|
|
|
Improved execution speed: Four byte instruction queue
|
|
Powerful interrupt function
|
|
Automatic data transfer function (does not use instructions): Internal peripherals
|
|
RAM: 1 Kbyte (MB90611A) 3 Kbytes (MB90613A)
|
|
General purpose ports 8, 16-bit data bus, multiplexed mode:
|
57 ports max.
|
|
16-bit non-multiplexed mode : 41 ports max.
|
|
8-bit non-multiplexed mode : 49 ports max.
|
|
|
UART (SCI): 3 channels for either asynchronous or clocked serial transfer (I/O expansion serial)
|
|
A/D converter: 8 channels (10-bit): 8-bit conversion mode also available
|
|
PPG (programmable pulse generator): 2 channels
|
|
16-bit reload timer: 2 channels
|
|
Chip select output: 8 channels
|
|
External interrupts: 8 channels
|
|
18-bit timebase timer
|
|
Watchdog timer function
|
|
PLL clock multiplier function
|
|
CPU intermittent operation function
|
|
Various standby modes
|
|
LQFP-100/QFP-100 package
|
|
CMOS technology
|
