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F²MC-16L CPU
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Minimum execution time: 62.5 ns/4 MHz oscillation (uses PLL multiplier): fastest speed at quadruple operation
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Instruction set optimized for controller applications
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Upward compatibility at object level with the F²MC-16(H)
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Various data types (bit, byte, word, long-word)
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Higher speed due to review of instruction cycle
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Expanded addressing modes: 23 types
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High coding efficiency
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Two access methods (bank system or linear pointer)
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Improved multiply-and-divide instructions (additional signed instructions)
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Improved high-precision operation with 32-bit accumulator
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Extended intelligent I/O services (access area extended by 64 Kbytes)
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Large memory space: 16 Mbytes
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Improved instruction set applicable to high-level language (C) and multitasking
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System stack pointer
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Improved indirect instructions using various pointers
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Barrel shift instruction
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Stack check function
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Improved execution speed: 4-byte instruction queue
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Improved interrupt functions
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Automatic data transfer function independent of CPU: Peripheral Resources
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ROM: 16 Kbytes (MB90661A), 32 Kbytes (MB90662A), 48 Kbytes (MB90663A)
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One-time PROM: 48 Kbytes (MB90P663A)
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RAM: 512 bytes (MB90661A), 1.64 Kbytes (MB90662A), 2 Kbytes (MB90663A/MB90P663A)
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General-purpose ports: Max. 51
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UART: 1 channel can be used for both asynchronous transfer and clocked serial (I/O extended serial) communications
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A/D converter: 10-bit, 8 channels includes 8-bit conversion mode
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16-bit reload timer: 4 channels
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8-bit PWM: 1 channel
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External interrupts: 8 channels
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18-bit timebase timer with watchdog timer function
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PLL clock multiplier function
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CPU intermittent operation function
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Various standby modes
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Package: SH-DIP-64/LQFP-64 (0.65-mm pitch)
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CMOS technology
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