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Clock
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Embedded PLL clock multiplication circuit
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Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
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Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at Vcc of 5.0 V)
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CPU addressing space of 16 Mbytes
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Internal addressing of 24-bit
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External accessing can be performed by selecting 8/16-bit bus width (external bus mode)
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Instruction set optimized for controller applications
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Rich data types (bit, byte, word, long word)
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Rich addressing mode (23 types)
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High code efficiency
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Enhanced precision calculation realized by the 32-bit accumulator
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Instruction set designed for high level language (C) and multi-task operations
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Adoption of system stack pointer
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Enhanced pointer indirect instructions
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Barrel shift instructions
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Enhanced execution speed: 4-byte instruction queue
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Enhanced interrupt function: 8 levels, 32 factors
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Automatic data transmission function independent of CPU operation: Extended intelligent I/O service function (EI²OS)
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Low-power consumption (standby) mode
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Sleep mode (mode in which CPU operating clock is stopped)
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Timebase timer mode (mode in which other than oscillation and timebase timer are stopped)
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Stop mode (mode in which oscillation is stopped)
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CPU intermittent operation mode
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Hardware standby mode
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Process: CMOS technology
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I/O port
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MB90670 series: Maximum of 65 ports
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MB90675 series: Maximum of 84 ports
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Timer
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Timebase timer/watchdog timer: 1 channel
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8/16-bit PPG timer: 8-bit x 2 channels or 16-bit x 1 channel
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16-bit reload timer: 2 channels
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24-bit free-run timer: 1 channel
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Input capture (ICU): Generates an interrupt request by latching a 24-bit free-run timer counter value upon detection of an edge input to the pin.
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Output compare (OCU): Generates an interrupt request and reverse the output level upon detection of a match between the 24-bit free-run timer counter value and the compare setting value.
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I²C interface (in MB90675 series only): Serial I/O port for supporting Inter IC BUS
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UART0
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With full-duplex double buffer (8-bit length)
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Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used.
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UART1 (SCI)
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With full-duplex double buffer (8-bit length)
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Clock asynchronized or clock synchronized serial transmission (I/O extended serial) can be selectively used.
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DTP/external interrupt circuit (4 channels): A module for starting extended intelligent I/O service (EI²OS) and generating an external interrupt triggered by an external input.
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Wake-up interrupt: Receives external interrupt requests and generates an interrupt request upon an "L" level input.
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Delayed interrupt generation module: Generates an interrupt request for switching tasks.
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8/10-bit A/D converter (8 channels)
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8-bit or 10-bit resolution can be selectively used.
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Starting by an external trigger input.
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