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32-bit RISC, load/store architecture, 5-stage pipeline
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Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
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General purpose registers: 32 bits * 16
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16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
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Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
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Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages
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Register interlock functions, efficient assembly language coding
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Branch instructions with delay slots: Reduced overhead time in branch executions
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Internal multiplier/supported at instruction level
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Signed 32-bit multiplication: 5 cycles
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Signed 16-bit multiplication: 3 cycles
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Interrupt (push PC and PS): 6 cycles, 16 priority levels: External bus interface
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Clock doubler: Internal 50 MHz, external bus 25 MHz operation
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25-bit address bus (32 Mbytes memory space)
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8/16-bit data bus
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Basic external bus cycle: 2 clock cycles
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Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6
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Interface supported for various memory technologies: DRAM interface (area 4 and 5)
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Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
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Unused data/address pins can be configured us input/output ports
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Little endian mode supported (Select 1 area from area 1 to 5): DRAM interface
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2 banks independent control (area 4 and 5)
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Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM
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Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
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Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
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DRAM refresh
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CBR refresh (interval time configurable by 6-bit timer)
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Self-refresh mode
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Supports 8/9/10/12-bit column address width
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2CAS/1WE, 2WE/1CAS selective: Cache memory
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1-Kbyte instruction cache memory
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32 block/way, 4 entry(4 word)/block
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2 way set associative
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Lock function: For specific program code to be resident in cashe memory: DMA controller (DMAC)
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8 channels
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Transfer incident/external pins/internal resource interrupt requests
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Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
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Transfer data length: 8 bits/16 bits/32 bits selective
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NMI/interrupt request enables temporary stop operation UART
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3 independent channels
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Full-duplex double buffer
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Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
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Asynchronous (start-stop system), CLK-synchronized communication selective
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Multi-processor mode
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Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate
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Use external clock can be used as a transfer clock
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Error detection: Parity, frame, overrun
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