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32-bit RISC, load/store architecture, 5-stage pipeline
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Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
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General purpose registers: 32 bits x 16
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16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
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Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
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Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages
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Register interlock functions, efficient assembly language coding
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Branch instructions with delay slots: Reduced overhead time in branch executions
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Internal multiplier/supported at instruction level
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Signed 32-bit multiplication: 5 cycles
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Signed 16-bit multiplication: 3 cycles
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Interrupt (push PC and PS): 6 cycles, 16 priority levels
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