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FR30CPU
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32-bit RISC, load/store architecture, and five-stage pipeline
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Operating frequency: 25 MHz outside and 50 MHz inside
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General-purpose register: 32 bits x 16
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16-bit fixed-length instructions (basic instructions), one instruction/cycle
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Instructions suitable for built-in control: Inter-memory transfer, bit processing, and barrel shift
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High-level language instructions: Function entry/exit and register contents multi-load/store
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Register interlock function: Making assembler descriptions easy
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Branch instruction with delayed slot: Reducing the overhead at branching
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Built-in multiplier: Support on the instruction level
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Signed 32-bit multiplication: 5 cycles
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Signed 16-bit multiplication: 3 cycles
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Interrupt (PC and PS save): 6 cycles, 16 priority levels
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Bus interface
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24-bit address bus (16MB space)
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Operating frequency: 25 MHz
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16/8-bit data bus
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Basic external bus cycle: 2 clock cycles
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Chip select outputs that can be set in the minimum units of 64 Kbytes: 6
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Memory interface support
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DRAM interface (Areas 4 and 5)
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Automatic wait cycle: Arbitrary setting from 0 to 7 cycles for each area
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Unused data/address pin available as an I/O port
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Little endian mode supported (One selected area from 1 to 5)
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I-RAM: 16KB
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DRAM interface
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Two-bank independent control (Areas 4 and 5)
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Ordinary mode/High-speed page mode
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Basic bus cycle: 5 in ordinary mode and 1 in high-speed page mode
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Programmable waveform: Automatic one-cycle wait insertion into RAS and CAS
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DRAM refresh
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CBR refresh (Arbitrary interval setting using the 6-bit timer)
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Self-refresh mode
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8, 9, 10, or 12 column addresses
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2CAS/1WE or 2WE/1CAS selectable
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Cache memory
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1KB instruction cache
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Two-way set associative
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32 blocks/way or 4 entries (4 words)/block
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Lock function (Keeping specific program codes resident in a cache)
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DMA controller (DMAC)
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5 channels
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Out --> out: 2.5 access cycles/transfer (2 clock cycles = 1 access cycle)
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In --> out: 1.5 access cycles/transfer (2 clock cycles = 1 access cycle)
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Address register (increment, decrement, and reload feasible): 32 bits x 5 channels
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Transfer count register (reload feasible): 16 bits x 5 channels
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Transfer sources: External pin, internal resource, and software interrupt
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Transfer sequences
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Step or block transfer
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Burst or continuous transfer
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Transfer data length: 8, 16, or 32 bits selectable
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Pause by NMI or interrupt request
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UART
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Full-duplex double buffer
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Data length: 7 to 9 bits (with no parity) or 6 to 8 bits (with parity)
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Synchronous system: Asynchronous (step-synchronous) or CLK synchronous selectable
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Multiprocessor mode
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Built-in baud rate generator
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External clock available as transfer clock
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Baud rate clock output possible
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Error detection: Parity, frame, and overrun errors
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PPG timer
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Frequency or duty setting register: 16 bits x 6 channels
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PWM function: One-shot function selectable
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Activation: Software or external trigger selectable
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A/D converter (Successive conversion)
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10-bit resolution, 8 channels
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Successive approximation: 5.6µs at 25 MHz
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Built-in sample &hold circuit
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Conversion mode: Single, scan, or repetitive conversion selectable
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Activation: Software, external trigger, or internal timer selectable
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Reload timer
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16-bit timer: 2 channels
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Internal clock: Two-clock-cycle resolution, number of divisions selectable from 2, 8, and 32
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Pin input: Event counter input/gate function
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Square wave output
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Other interval timer
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Watchdog timer: 1 channel
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Bit search module
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Searching the position of the first "1"/"0" change bit from the MSB in a word
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Interrupt controller
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External interrupt input: Non-maskable interrupt (NMIX), ordinary interrupt x 8 (INT0 to INT7)
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Internal interrupt sources: UART, DMAC, A/D, reload timer, PPG timer, and delayed interrupt
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The priorities of interrupts, excepting a non-maskable interrupt, can be set to 16 levels by programming.
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Reset sources
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Power-on reset, hardware standby, watchdog timer, software reset, and external reset
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Low-power consumption mode
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Sleep and stop
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Clock control
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Gear function: The CPU and peripheral operation clock frequencies can be set independently.
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The gear clock can be selected from 1/1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16).
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Other
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Package: LQFP-144
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CMOS technology: 0.35µm
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Power supply: 5.0 V ± 10%, 3.3 V ± 5%
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