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FR-CPU
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32-bit RISC (FR30), load/store architecture, 5-stage pipeline
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Operating frequency: Internal 25 MHz [external 25 MHz] (source oscillation 12.5 MHz with PLL used)
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General-purpose registers: 32 bits x 16
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16-bit fixed-length instructions (basic instructions), one instruction per cycle
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Inter-memory transfer, bit processing, and barrel shift instructions, which are suitable for embedding applications
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Function entry/exit instructions and register data multiload/store instructions, which are compliant with high-level language instructions
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Register interlock function, which eases assembler coding
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Branch instruction with delay slot, which reduces overheads in branch processing
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Built-in adder, supported in the instruction level
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Signed 32-bit addition: 5 cycles
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Signed 16-bit addition: 3 cycles
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Interrupt (PC, PS saving): 6 cycles, 16 priority levels
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Bus interface
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Operating frequency: Up to 25 MHz (internal), 25 MHz (external bus)
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25-bit address bus (32-megabyte address space)
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16-bit address output, 8-bit or 16-bit data input and output
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Basic bus cycle: 2 clock cycles
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Chip Select output that can be set in 64 kilobytes minimum: 6 lines
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Interface support for each type of memory
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DRAM interface (areas 4 and 5)
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Automatic wait cycle: Any number of cycles (0 to 7) can be set for each area.
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Unused data and address terminals can be used as I/O ports.
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Support for little endian mode (selecting one of areas 1 to 5)
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DRAM interface
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2-bank independent control (areas 4 and 5)
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Double CAS DRAM (normal DRAM interface), single CAS DRAM, and hyper DRAM
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Basic bus cycle: Five cycles in normal mode. Two-cycle access is enabled in high-speed page mode.
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Programmable waveform: Automatic 1-cycle wait can be inserted into RAS or CAS.
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DRAM refresh
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CBR refresh (The interval can be set as desired using the 6-bit timer.)
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Self-refresh mode
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Support for 8-, 9-, 10-, or 12-line column address
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Choice between 2CAS/1WE and 2WE/1CAS
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DMAC (DMA controller)
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Eight channels
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Transfer cause: External terminal or internal resource interrupt request
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Transfer sequence
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Step transfer or block transfer
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Burst transfer or continuous transfer
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Transfer data length: Selectable from 8, 16, and 32 bits
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A temporary stop is enabled by an NMI/interrupt request.
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UART
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Independent three channels
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Full duplex double buffer
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Data length: 7 to 9 bits (no parity) or 6 to 8 bits (with parity)
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Choice between asynchronous (start-stop synchronization) communication and clock asynchronous communication
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Multiprocessor mode
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Built-in 16-bit timer (U-Timer) as a baud rate generator, which can generate a desired baud rates
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An external clock can be used as a transfer clock.
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Error detection: Parity error, frame error, and overrun
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A/D converter (successive approximation conversion type)
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10-bit resolution, 4 channels
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Successive approximation conversion type: 5.6µs at 25 MHz
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Built-in sample and hold circuit
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Conversion mode: Selectable from single conversion, scan conversion, and repeat conversion
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Starting: Selectable from software, external trigger, and internal timer
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Reload timer
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16-bit timer: Three channels
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Internal clock: 2-clock cycle resolution. Selectable from 2-, 8-, and 32-frequency division mode
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Other interval timers
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16-bit timer: Three channels (U-Timer)
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PWM timer: Four channels
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Watchdog timer: One channel
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Bit search module
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Searches for the bit position that first changes between 1 and 0 beginning from MSB of a word in one cycle.
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Interrupt controller
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External interrupt input: Nonmaskable interrupt, normal interrupt x 4 (INT0 to INT3)
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Internal interrupt causes: UART, DMAC, A/D, reload timer, PWM, UTIMER, and delayed interrupt
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Up to 16 priority levels are programmable for interrupts other than nonmaskable interrupts.
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Reset types
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Power-on reset, watchdog timer reset, software reset, and external reset
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Power save mode
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Sleep/stop mode
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Clock control
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Gear function: Desired operating clock frequencies can be set for the CPU and peripherals independently. A gear clock can be selected from 1/1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16). However, the operating clock frequency for peripherals cannot exceed 25 MHz.
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Others
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Packages: QFP-100, LQFP-100, FBGA-112
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CMOS technology: 0.5µm
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Power supply: 3.3 V plus or minus 0.3 V
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254-kilobyte flash ROM: Can be read, written, and erased by a single power supply.
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