MCAN Initialization Routine

*
        LDA     #RIE|OIE|EIE|RR  ;set up CAN control register:
        STA     CCNTRL  ;enable Receive/Overrun/Error interrupts,
*                       only rec. to dom. edge for synchronization,
*                       reset request present,
        LDA     #$FF
        STA     CACM    ;accept all IDs-->no need to initialize CACC
*
        LDA     #$58
        STA     CBT1    ;Set up bus timing reg. 1
*                        125 kBaud -> 8 ms bit time 
*                        with 4 MHz crystal 
*                        for P=1: 1tSCL = 1Tq = 0.5 ms
*                         -->BT = 16 x tSCL
*                        choosen: tSEG1 = 9 x tSCL
*                                 tSEG2 = 6 x tSCL
*                                 tSYNC = 1 x tSCL
        LDA     #$C0
        STA     CBT0    ;Set up bus timing reg. 0
*                       P=1 --> tSCL = 0.5 ms
*                       tSJW = 4 x tSCL
*
        LDA     #$FA
        STA     COCNTRL ;Set output control register
*                       Normal mode 1,
*                       OCTP0 = OCTN0 = 1
*                       OCTP1 = OCTN1 = 1
*                       --> drivers Tx0 and Tx1 push/pull
*                       -->both NTrans and PTrans enabled
*                       OCPOL0 = 0, OCPOL1 = 1,
*                       Tx0 Tx'ed normally, Tx1 inverted
        LDA     CCNTRL
        AND     #$FE    ;Set up CAN control reg.
        STA     CCNTRL  ;set reset request absent
*
        LDA     CCOMCPY ;load a copy of CCOM register in RAM
        ORA     #CMPSEL ;setup sleep comparator for
        STA     CCOM     ;two line mode
        STA     CCOMCPY  ;save CCOM register (write only)
*
NOBS    LDA     CSTAT   ;check receive/Transmit state for bus idle
        AND     #$30    ;bus is idle, if TS and RS equals 0
        BNE     NOBS    ;wait until bus is idle
        BRS     WAIT88  ;if bus is idle, then count 11 consecutive bits
                        ;which is 88 ms at 125 kbaud bus speed
RTS