Clock Generator Circuits

PLL
The phase-locked loop (PLL) is a frequency generator that takes an input clock frequency and multiples it to a much higher frequency. The 68HC08 has two different PLL modules, one uses a 32Khz crystal as its input and another uses a 1 - 4 Mhz crystal. Both versions generate the internal clocks used to support 8Mhz bus operation. Without the PLL, 68HC08s would require a 32Mhz oscillator which is expensive and can potentially generate unwanted noise in the MCU application. The 68HC05 has several different PLL modules used to generate the high frequencies needed for on screen displays and closed-captioning.

CGM
The Clock Generator Module (CGM) is a 68HC08 module that generates two different clock signals from a user-selected source. The crystal clock signal is buffered by the CGM and used by the SCI baud rate generator and the COP watchdog timer. In addition, the output clock of the CGM, generated by either the crystal clock or an on-board phased-lock loop clock, is used by the SIM, which drives internal bus clocks. The on-board phased-lock loop can be used to generate maximum bus speed (8 MHz) cost-effectively (1 MHz to 16 MHz external crystal).

last update: 10JUL1997