Addressing Modes — INH
The operand of an instruction that uses inherent addressing is implied by or inherent in the instruction’s opcode.
Some instructions explicitly name registers…
ASLA, CLRX, DECA, INCX, ROLA, RORX, RSP, TAX, TXA
Others explicitly name condition code register bits…
Still others affect one or more unnamed registers…
MUL, RTI, RTS, STOP, SWI, WAIT
And some have no operands whatsoever…
Notes:
Instructions that use inherent addressing need only one byte of program storage. These are the simplest 68HC05 instructions because they have fixed operands.
Any instruction that operates directly on a named register without an attendant read or write cycle uses inherent addressing. ASLX, CLRA, DECX, INCA, RSP, and TXA are obvious examples. The same also applies to the CLC, CLI, SEC, and SEI instructions that directly manipulate condition code register bits.
Inherent mode instructions that do not explicitly name registers typically affect multiple registers or a single condition code register bit. MUL, for example, uses the accumulator and the index register. SWI and RTI operate on all of the CPU registers, while STOP and WAIT only clear the condition code register interrupt mask (I) bit.
Instructions that use inherent addressing can have no other addressing modes, only analogous instructions that use other addressing modes. For example, LSLA, LSLX, and LSL all perform a logical shift left. LSLA operates only on the accumulator, LSLX only on the index register, and LSL only on a memory location.