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Log: 
0.1 Steve Trynosky 12/15/2000
	- initial release
	- uses Synopsys MPC740_FX bus functional model
	- uses Micron Semiconductor SSRAM Verilog model

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====================
Design Description:
====================

The PowerPC 60X Bus Interface controller is designed and targeted towards a 
Virtex-E XCV400-8-BG432 device. The -7 and -6 speed devices can also be used, 
however the clock rate decreases with slower devices. The design is simulated
using a Synopsys MPC740_FX bus functional processor model and a Micron SSRAM 
memory model. Modelsim_SE is required for Synopsys FlexModel simulation.

===============
Design Status:
===============
As of December 15, 2000, the Verilog design files DO NOT have the clock DLL 
circuitry and some other timing improvements. The VHDL design includes a 
clock DLL circuit, and all 60X bus I/O has been registered to meet bus timing 
constraints. Registered I/O is extremely important in order to meet increasing 
60X bus clock speeds. The Verilog design is in the process of being updated to 
include the timing solutions implemented in the VHDL design.


==================
Design Hierarchy:
==================

st_mpc750_tst		(top level)
  top_60x		(60x bus interface controller)	
    adr_arb		(address arbiter)
    adrpipe 		(address and transfer qualifier decoder)
    dataflow		(data bus arbiter and pipeline control)
    databus		(data bus interface, tristate controls)
    sramctl		(SSRAM memory controller state machine)
    flash_if		(Flash memory controller and data assembler)
  mt58l256l36f		(Micron SyncBurst SSRAM memory model)
  pullup		(Verilog behavioral simulation pullups)
  pullups		(Verilog behavioral simulation pullups)


=======
Files:
=======

The files have been structured into four separate *.zip files. There is a separate
zip file for the Place and Route text files, the Verilog design, the VHDL design, 
and the ModelSim_SE sample waveform PDF files.


Design Files:

Verilog: (see xapp246_verilog.zip file)
  
    adr_arb.v
    adrpipe.v
    databus.v
    dataflow.v
    flash_if.v
    sramctl.v
    top_60x.v

VHDL: (see xapp246_vhdl.zip file)
 
    adr_arb.vhd
    adrpipe.vhd
    databus.vhd
    dataflow.vhd
    flash_if.vhd
    sramctl.vhd
    top_60x.vhd

Design verification files: (see xapp246_verilog.zip file)
    mt58l256l36f.v	(SSRAM memory model)
    pullup.v		(behavioral simulation, use bus keepers in FPGA)
    pullups.v		(behavioral simulation, use bus keepers in FPGA)
    st_mpc750_tst.v	(top level testbench)

ModelSim_SE5.4d Simulation waveform (PDF files)

The following PDF files can be viewed using the Adobe Acrobat Reader. These files
show some representative bus cycles produced by the testbench and show SSRAM read 
or write accesses of the reference design.Single beat and four beat cycles are
demonstrated.

    (see xapp246_waves.zip for the following files)

    st_mpc750_1bw_8x_wave.pdf		(single byte write, each byte lane)
    st_mpc750_2bw_4x_wave.pdf		(two byte write, four times)
    st_mpc750_3bw1bw_8x_wave.pdf	(misaligned 3byte, 1byte write)
    st_mpc750_4bw_4x_wave.pdf		(four byte writes)
    st_mpc750_4w4r_wave.pdf		(4 beat write and 4 beat read)
    st_mpc750_8bw_4x_wave.pdf		(1 beat write, four times)
  	
Synthesis output EDIF Netlist(from VHDL design): (see xapp246_routing.zip file)
    top_60x.edf	

Place and Route Timing Constraints(for Verilog or VHDL design):

The timing constraints include the system clock frequency, 60X bus inputs and 
outputs, SSRAM memory I/O and control, 60X bus control input pullups, databus 
keepers, and various IO Standards. The LVCMOS2 bus standard is used for the 
60X bus and the LVTTL standard is used for the memory interface.

    top_60x.ucf (see xapp246_routing.zip file)

Other post place and route files: (see xapp246_routing.zip file)

    fe.log
    map.mrp
    top_60x.dly
    top_60x.pad
    top_60x.par
    top_60x.twr
    time_sim.sdf


============================
Frequently Asked Questions:
============================
Q. What are the delays in the source code for?
A. The delays are used to simulate logic or routing delays and to prevent setup 
and hold violations during functional simulation. These delays are replaced 
with actual delays in post place and route simulation. Most synthesis tools 
should ignore the behavioral delays.

Q. Why aren't there any design verification files for the VHDL design?
A. The design was simulated using the ModelSim_SE simulator which supports mixed 
mode (Verilog and VHDL design) simulation. The design was verified using the 
Verilog design language and then converted to VHDL.
