74ACT11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS061A - D2957, JULY 1987 - REVISED APRIL 1993

Copyright © 1992, Texas Instruments Incorporated

features

• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C

EPIC is a trademark of Texas Instruments Incorporated.

description

These devices consist of bus transceiver circuits, 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B bus will be clocked into the registers on the low-to-high transition of the appropriate clock pin (CAB or CBA). Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers.

Enable (G\) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for select control will eliminate the typical decoding glitch which occurs in a multiplexer during the transition between stored and real-time data. The direction control determines which bus will receive data when enable G\ is active (low). In the isolation mode (control G\ high), A data may be stored in one register and/or B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time.

The 74ACT11646 is characterized for operation from - 40°C to 85°C.