74ACT11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET

SCAS064A - D3339, JUNE 1989 - REVISED APRIL 1993

Copyright © 1992, Texas Instruments Incorporated

features

• Inputs Are TTL-Voltage Compatible
• Fully Buffered to Offer Maximum Isolation From External Disturbance
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

EPIC is a trademark of Texas Instruments Incorporated.

description

This device contains two independent J-K negative-edge-triggered flip-flops. A low level at the or input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The 74ACT11112 is characterized for operation from - 40°C to 85°C.