54AC11112, 74AC11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET

SCAS073A - JUNE 1989 - REVISED APRIL 1993

Copyright © 1993, Texas Instruments Incorporated

features

• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configuration Minimizes High-Speed Switching Noise
• EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015
• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

EPIC is a trademark of Texas Instruments Incorporated.

description

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The 54AC11112 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74AC11112 is characterized for operation from -40°C to 85°C.