74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS

SCAS088A - DECEMBER 1989 - REVISED APRIL 1996

features

• Independent Registers and Enables for A and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-um Process
• 500-mA Typical Latch-Up Immunity at 125°C

EPIC is a trademark of Texas Instruments Incorporated.

description

The 74AC11652 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and ) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11652.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.

The 74AC11652 is characterized for operation from -40°C to 85°C.