74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER

SCAS105A - FEBRUARY 1990 - REVISED APRIL 1993

Copyright © 1993, Texas Instruments Incorporated

features

• Single Down/Up Count Control Line
• Look-Ahead Circuitry Enhances Speed of Cascaded Counters
• Fully Synchronous in Count Modes
• Asynchronously Presettable with Load Control
• Flow-Through Architecture to Optimize PCB Layout
• Center-Pin V_CC and GND Configurations to Minimize High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

EPIC is a trademark of Texas Instruments Incorporated.

description

The 74AC11191 is a synchronous, 4-bit binary reversible up/down counter. Synchronous counting operation is provided by clocking all flip-flops simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.

The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input () is low. A high at inhibits counting. The direction of the count is determined by the level of the down/up (D/U\) input. When D/U\ is low, the counter counts up and when D/U\ is high, it counts down.

These counters feature a fully independent clock circuit. Changes at the control inputs ( and D/U\) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condition meeting the stable setup and hold times.

These counters are fully programmable; that is, the outputs may be preset to any number between 0 and 15 by placing a low on the load input and entering the desired data at the data inputs. The outputs will change to agree with the data inputs independently of the level of the clock input. This feature allows the counter to be used as a modulo-N divider by simply modifying the count length with the preset inputs.

Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. The ripple-clock output () produces a low-level output pulse under those same conditions but only while the clock input is low. The counter can easily be cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.

The 74AC11191 is characterized for operation from - 40°C to 85°C.