74AC11648
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS114 - MARCH 1990 - REVISED APRIL 1993

Copyright © 1993, Texas Instruments Incorporated

features

• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

EPIC is a trademark of Texas Instruments Incorporated.

description

The 74AC11648 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal

registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11648.

Output-enable and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus will receive data when is low. In the isolation mode ( high), A data may be stored in one register and/or B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time.

The 74AC11648 is characterized for operation from -40°C to 85°C.