74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS135 - MARCH 1990 - REVISED APRIL 1993

Copyright © 1993, Texas Instruments Incorporated

features

• Independent Registers and Enables for A and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

EPIC is a trademark of Texas Instruments Incorporated.

description

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and ) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11651.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and . In this configuration, each output reinforces its input. Thus, when all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.

The 74AC11651 is characterized for operation from -40°C to 85°C.