54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCAS156A - NOVEMBER 1990 - REVISED APRIL 1993

features

• Inputs Are TTL-Voltage Compatible
• Provides Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Ceramic 300-mil DIPs

  EPIC is a trademark of Texas Instruments Incorporated.

   

description

These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

On the positive transition of the clock the Q outputs will follow the D inputs.

A buffered output enable () input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components.

The output enable ()does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The 54ACT11821 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT11821 is characterized for operation form -40°C to 85°C.