SN54ACT8999, SN74ACT8999
SCAN-PATH SELECTORS WITH 8-BIT BIDIRECTIONAL DATA BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP MULTIPLEXERS

SCAS158D - JUNE 1990 - REVISED DECEMBER 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Members of theTexas Instruments SCOPE^TM Family of Testability Products
• Compatible With the IEEE Standard 1149.1 (JTAG) Serial Test Bus
• Allow Partitioning of System Scan Paths
• Can Be Cascaded Horizontally or Vertically
• Select One of Four Secondary Scan Paths to Be Included in a Primary Scan Path
• Provide Communication Between Primary and Remote Test Bus Controllers
• Include 8-Bit Programmable Binary Counter to Count or Initiate Interrupt Signals
• Include 8-Bit Identification Bus for Scan Path Identification
• Inputs Are TTL Compatible
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

   

  SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
  

description

The 'ACT8999 are members of the Texas Instruments SCOPE^TM testability integrated-circuit family. This family of components facilitates testing of complex circuit-board assemblies.

The 'ACT8999 enhance the scan capability of TI's SCOPE^TM family by allowing augmentation of a system's primary scan path with secondary scan paths (SSPs), which can be individually selected by the 'ACT8999 for inclusion in the primary scan path. The device also provides buffering of test signals to reduce the need for external logic.

By loading the proper values into the instruction register and data registers, the user can select one of four secondary scan paths. This has the effect of shortening the scan path to allow maximum test throughput when an individual subsystem (board or box) is to be tested. Any of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.

All operations of the device except counting are synchronous to the test clock (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) and output interrupt signals via the device condition output (DCO). The device can be configured to count on either the rising or falling edge of DCI.

If a system's test architecture contains more than one test bus controller, the 8-bit bidirectional bus can be used to interface a higher-level primary bus controller (PBC) with one or more lower-level remote bus controllers (RBCs). A protocol allows the PBC to pass control of the 'ACT8999 to an RBC, freeing the PBC for other tasks. The 8-bit bus also can be hardwired to provide one of 256 codes for subsystem identification. The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.

The SN54ACT8999 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8999 is characterized for operation from 0°C to 70°C.