74ACT11160
SYNCHRONOUS 4-BIT DECADE COUNTER

SCAS170 - D3624, AUGUST 1990 - REVISED APRIL 1993

features

• Inputs Are TTL-Voltage Compatible
• Internal Look-Ahead for Fast Counting
• Carry Output for N-Bit Cascading
• Fully Synchronous Operation for Counting
• Synchronously Programmable
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

  EPIC is a trademark of Texas Instruments Incorporated.

description

This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock-input waveform.

This counter is fully programmable; that is, it may be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load () input disables the counter and causes the outputs to agree with the setup data after the next clock rising edge regardless of the levels of the enable inputs. The clear function for the 74ACT11160 is asynchronous, and a low level at the clear () input sets all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output. Both count-enable inputs must be held high to count, and ENT is fed forward to enable RCO. RCO thus enabled will produce a high-level pulse while the count is 9 (HLLH). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input.

This counter features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or ) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times.

The 74ACT11160 is characterized for operation from -40°C to 85°C.