SN74ACT7803
512 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS191A - MARCH 1991 - REVISED JULY 1995

features

• Member of the Texas Instruments Widebus^TM Family
• Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
• Read and Write Operations Synchronized to Independent System Clocks
• Input-Ready Flag Synchronized to Write Clock
• Output-Ready Flag Synchronized to Read Clock
• 512 Words by 18 Bits
• Low-Power Advanced CMOS Technology
• Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
• Bidirectional Configuration and Width Expansion Without Additional Logic
• Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
• Data Rates From 0 to 67 MHz
• Pin Compatible With SN74ACT7805 and SN74ACT7813
• Available in Shrink Small-Outline 300-mil (DL) Package Using 25-mil Center-to-Center Spacing

  Widebus and OEC are trademarks of Texas Instruments Incorporated.

   

description

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous data paths at 67-MHz clock rates and 12-ns access times. Its 56-pin shrink small-outline package (DL) offers greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed V_CC and GND pins along with TI's patented output-edge-control (OEC^TM) circuit dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high,is low, and IR is high. Data is read from memory on the rising edge of RDCLK when,, andare low and OR is high. The first word written to memory is clocked through to the output buffer regardless of the,, andlevels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK.must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and HF flags low and the AF/AE flag high. The FIFO must be reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.