SN74ACT8994
DIGITAL BUS MONITOR
IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SCAS196E - JULY 1990 - REVISED DECEMBER 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Member of the Texas Instruments SCOPE^TM Family of Testability Products
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• Contains a 1024-Word by 16-Bit Random-Access Memory (RAM) to Store the States of a Digital Bus
• Test Operations Are Synchronous to the Test Clock or System Clock(s)
• Contains Texas Instruments Event Qualification Module for Real-Time System Test
• Eight Protocols for On-Line Signal Monitoring and Test Operations
• Inputs Are TTL-Voltage Compatible
• Performs Parallel-Signature Analysis (PSA) of Data Inputs With User-Definable Feedback
• Data Inputs Are Maskable During PSA Operations
• Cascaded PSA Mode Allows Compression of Parallel Data Paths Greater Than 16 Bits in Width
• Direct Memory Access (DMA) Speeds Memory and Register File Read/Write Operations
• Power-Down Mode When RAM Is Idling Reduces Power Dissipation
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• Packaged in 28-Pin Plastic Chip Carriers

  SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

   

description

The SN74ACT8994 digital bus monitor (DBM) is a member of the Texas Instruments SCOPE^TM testability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The DBM is a boundary-scannable device designed to monitor and/or store the values of a digital bus up to 16 bits in width. It resides in parallel with the bus being monitored.

Data at the D-input pins can be stored in a scannable random-access memory (RAM). Up to 1024 words of 16 bits can be stored. A parallel-signature analysis (PSA) can be performed on the data or on the contents of memory. The PSA operations use a linear-feedback shift-register technique to compress data into a signature. The user can configure the device to mask any combination of data inputs and control the feedback used during PSA operations.

The DBM receives instructions via the IEEE Standard 1149.1-1990 test access port (TAP) interface. The TAP interface consists of test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) pins.

The DBM can be operated in the off-line mode or the on-line mode. In the off-line mode, the device performs test operations independent of system conditions. Off-line test operations include parallel-signature analysis (PSA) on the contents of RAM and external test.

In the on-line mode, the DBM can be configured to perform test operations that are initiated based on system conditions and that operate synchronously to a logical combination of one or more system clocks. The device allows sample, storage, and/or PSA operations to be performed according to one of eight protocols. Compare patterns, which can be stored in the event-qualification module (EQM), allow the user to define specific values of the 16-bit bus for which the test operations are to be performed.

The 1024-word by 16-bit RAM and the EQM register files can be serially accessed using IEEE-Standard-1149.1-1990-compatible read and write instructions. However, direct memory access (DMA) instructions also are provided to speed transfer of large amounts of data to and from the RAM and EQM.

The polynomial input/output (PIO) is a bidirectional pin used to cascade more than one DBM to provide signature analysis on a bus larger than 16 bits.

The SN74ACT8994 is characterized for operation from 0°C to 70°C.