SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

features

• Read and Write Clocks Can Be Asynchronous or Coincident
• Organization:
  • SN74ACT72211L - 512 × 9
  • SN74ACT72221L - 1024 × 9
  • SN74ACT72231L - 2048 × 9
  • SN74ACT72241L - 4096 × 9
• Write and Read Cycle Times of 15 ns
• Bit-Width Expandable
• Empty and Full Flags
• Programmable Almost-Empty and Almost-Full Flags With Default Offsets of Empty+7 and Full-7, Respectively
• TTL-Compatible Inputs
• Fully Compatible With the IDT72211/72221/72231/72241
• Available in 32-Pin Plastic J-Leaded Chip Carrier (RJ)

description

The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are constructed with CMOS dual-port SRAM and are arranged as 512, 1024, 2048, and 4096 9-bit words, respectively. Internal write and read address counters provide data throughput on a first-in, first-out (FIFO) basis. Full and empty flags prevent memory overflow and underflow, and two programmable flags (almost full and almost empty) are provided.

The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are synchronous FIFOs, which means the data input port and data output port each employ synchronous control. Write-enable (, WEN2/) signals allow the low-to-high transition of the write clock (WCLK) to store data in memory, and read-enable (, ) signals allow the low-to-high transition of the read clock (RCLK) to read data from memory. WCLK and RCLK are independent of one another and can operate asynchronously or be tied together for single-clock operation.

The empty-flag () output is synchronized to RCLK and the full-flag () output is synchronized to WCLK to indicate absolute boundary conditions. Write operations are prohibited when is low, and read operations are prohibited when is low. Two programmable flags, programmable almost empty () and programmable almost full (), can both be programmed to indicate any measure of memory fill. After reset, defaults to empty+7 and defaults to full-7. Flag-offset programming control is similar to a memory write with the use of the load (WEN2/) signal.

These devices are suited for providing a data channel between two buses operating at asynchronous or synchronous rates. Applications include use as rate buffers for graphics systems and high-speed queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit or packet-framing information.

The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are characterized for operation from 0°C to 70°C.