SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

features

• Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
• Two Independent 512 × 32 Clocked FIFOs Buffering Data in Opposite Directions
• Read Retransmit Capability From FIFO on Port B
• Mailbox-Bypass Register for Each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor Interface Control Logic
• IRA, ORA,, and Flags Synchronized by CLKA
• IRB, ORB, , and Flags Synchronized by CLKB
• Low-Power 0.8-Micron Advanced CMOS Technology
• Supports Clock Frequencies up to 67 MHz
• Fast Access Times of 11 ns
• Available in Space-Saving 120-Pin Thin Quad Flat (PCB) and 132-Pin Quad Flat (PQ) Packages

   

   

description

The SN74ACT3638 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512 × 32 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. The FIFO memory buffering data from port A to port B has retransmit capability, which allows previously read data to be accessed again. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 32-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths.

The SN74ACT3638 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The input-ready (IRA, IRB) flags and almost-full (, ) flags of the SN74ACT3638 are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flags and almost-empty (, ) flags of the SN74ACT3638 are two-stage synchronized to the port clock that reads data from its array. Offsets for the almost-full and almost-empty flags of both FIFOs can be programmed from port A.

The SN74ACT3638 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the application report FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories Designer's Handbook, literature number SCAA012A.