SN74ALVC16500
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCAS260 - JANUARY 1993 - REVISED MARCH 1994

features

• Member of the Texas Instruments Widebus^TM Family
• UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Designed to Facilitate Incident-Wave Switching for Line Impedances of 50-or Greater
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
• Bus-Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.

description

This 18-bit universal bus transceiver is designed for 2.7-V to 3.6-V V_CC operation.

Data flow in each direction is controlled by output-enable (OEAB and ), latch-enable (LEAB and LEBA), and clock ( and ) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if is held at a high or low logic level.If LEAB is low, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of . Output-enable OEAB is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses , LEBA, and . The output enables are complementary (OEAB is active high, and is active low).

The SN74ALVC16500 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74ALVC16500 is characterized for operation from -40°C to 85°C.