SN74ALVC16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS

SCAS267A - MARCH 1993 - REVISED MAY 1995

features

• Member of the Texas Instruments Widebus^TM Family
• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
• Bus Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

   

  EPIC and Widebus are trademarks of Texas Instruments Incorporated.

description

This 20-bit flip-flop is designed specifically for low-voltage (3.3-V) V_CC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V V_CC.

The SN74ALVC16721's 20 flip-flops are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable () input is low. If is high, no data is stored.

A buffered output-enable () input places the 20 outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.

The SN74ALVC16721 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74ALVC16721 is characterized for operation from -40°C to 85°C.