SN74ALVC16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS

SCAS276 - NOVEMBER 1993 - REVISED MARCH 1994


 

features

 

Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.

description

This 18-bit (dual-octal) noninverting registered transceiver is designed for 2.7-V to 3.6-V VCC operation.

The ´ALVC16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.

The ´ALVC16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable ( or) inputs. It also provides parity-enable () and parity-select (ODD/) inputs and separate error-signal (or) outputs for checking parity. The direction of data flow is controlled by and . When is low, the parity functions are enabled. When is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVC16901 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74ALVC16901 is characterized for operation from -40°C to 85°C.