SN74ALVC162820
3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTSAND SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS

SCAS278 - OCTOBER 1993 - REVISED MARCH 1994

features

• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Member of the Texas Instruments Widebus^TM Family
• Supports Unregulated Battery Operation Down to 2.7 V
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_CC Overshoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required.
• Bus-Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

  EPIC and Widebus are trademarks of Texas Instruments Incorporated.

description

This 10-bit flip-flop is designed specifically for low-voltage (3.3-V) V_CC operation

The flip-flops of the SN74ALVC162820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable () input does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include 26- resistors to reduce overshoot and undershoot.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVC162820 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74ALVC162820 is characterized for operation from -40°C to 85°C.