SCAS303C - JANUARY 1993 - REVISED JANUARY 1997
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This octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation.
The SN74LVC652A consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVC652A.
Data on the A or B data bus, or both, can be stored in the
internal D-type flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select-
or enable-control pins. When SAB and SBA are in the real-time
transfer mode, it is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and
. In this configuration, each
output reinforces its input. When all other data sources to the two
sets of bus lines are at high impedance, each set of bus lines
remains at its last state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor and OEAB should be tied
to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of
the driver.
The SN74LVC652A is characterized for operation from -40°C to 85°C.