CDC112
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER

SCAS322D - DECEMBER 1993 - REVISED APRIL 1996

features

• Low-Output Skew for Clock-Distribution and Clock-Generation Applications
• Differential Low-Voltage Pseudo ECL (LVPECL)-Compatible Inputs and Outputs
• Distributes Differential Clock Inputs to Nine Differential Clock Outputs
• Output Reference Voltage (V_REF) Allows Distribution From a Single-Ended Clock Input
• LVTTL-Compatible Output Enable
• Packaged in Plastic Chip Carrier

   

description

This differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, ) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.

When the output-enable () is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).

The V_REF output can be strapped to the input for a single-ended CLKIN input.

The CDC112 is characterized for operation from 0°C to 70°C.