CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

SCAS325A - JULY 1990 - REVISED NOVEMBER 1995

features

• Replaces SN74AS304
• Maximum Output Skew of 1 ns
• Maximum Pulse Skew of 1.5 ns
• TTL-Compatible Inputs and Outputs
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• Package Options Include Plastic Small-Outline (D) Package and Standard Plastic (N) 300-mil DIPs
  

description

The CDC304 contains eight flip-flops designed to have low skew between outputs. The eight outputs (in-phase with CLK) toggle on successive CLK pulses. Preset () and clear () inputs are provided to set the Q outputs high or low independent of the clock (CLK) input.

The CDC304 has output and pulse-skew parameters t_sk(o) and t_sk(p) to ensure performance as a clock driver when a divide-by-two function is required.

The CDC304 is characterized for operation from 0°C to 70°C.