CDC2586
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS337B - FEBRUARY 1993 - REVISED NOVEMBER 1995

features

• Low Output Skew for Clock-Distribution and Clock-Generation Applications
• Operates at 3.3-V V_CC
• Distributes One Clock Input to Twelve Outputs
• Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency
• No External RC Network Required
• External Feedback (FBIN) Synchronizes the Outputs to the Clock Input
• Application for Synchronous DRAM, High-Speed Microprocessor
• TTL-Compatible Inputs and Outputs
• Outputs Have Internal 26- Series Resistors to Dampen Transmission-Line Effects
• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Distributed V_CC and Ground Pins Reduce Switching Noise
• Packaged in 52-Pin Thin Quad Flat Package
  

  EPIC-IIB is a trademark of Texas Instruments Incorporated.

   

description

The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured for half-frequency operation. Each output has an internal 26- series resistor that improves the signal integrity at the load. The CDC2586 operates at nominal 3.3-V V_CC.

The feedback input (FBIN) synchronizes the output clocks in frequency and phase to CLKIN. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as feedback is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN frequency depending on which output is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at CLKIN.

Output-enable () provides output control. When is high, the outputs are in the high-impedance state. When is low, the outputs are active. is negative-edge triggered and can be used to reset the outputs operating at half frequency. TEST is used for factory testing of the device and can be used to bypass the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC2586 does not require external RC networks. The loop filter for the PLL is included on chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2586 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling of the PLL via TEST, and upon enable of all outputs via .

The CDC2586 is characterized for operation from 0°C to 70°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the CDC2586 PLL has a frequency range of 100 MHz to 200 MHz, twice the operating frequency range of the CDC2586 outputs. The output of the VCO is divided by two and four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The SEL0 and SEL1 inputs select which of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the frequency and phase of this output matches that of the CLKIN signal. In the case that a VCO/2 output is wired to FBIN, the VCO must operate at twice the CLKIN frequency resulting in device outputs that operate at either the same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at twice or the same as the CLKIN frequency.

output configuration A

Output configuration A is valid when any output configured as a 1 frequency output in Table 1 is fed back to FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs configured as 1/2 outputs operate at half the CLKIN frequency, while outputs configured as 1 outputs operate at the same frequency as CLKIN.

output configuration B

Output configuration B is valid when any output configured as a 1 frequency output in Table 2 is fed back to FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs configured as 1 outputs operate at the CLKIN frequency, while outputs configured as 2 outputs operate at double the frequency of CLKIN.